BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
X-LIC-LOCATION:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20260715T200610Z
LOCATION:DAC Pavilion\, Exhibit Floor
DTSTART;TZID=America/Los_Angeles:20260729T150000
DTEND;TZID=America/Los_Angeles:20260729T160000
UID:dac_DAC 2026_sess296_ENGPOST281@linklings.com
SUMMARY:Comprehensive SoC Power System Verification Using Optimized Mixed-
 Signal Verification Methodology
DESCRIPTION:Shibin Velluva (Microchip) and Neel Natekar (Siemens)\n\nPower
  systems are a critical component of the modern system on chips (SoCs) and
  present formidable mixed-signal verification challenges due to increasing
  design complexity and diverse power requirements. Designers face hurdles 
 like managing numerous power domains, operating modes, intricate power seq
 uencing, state transitions, and critical analog-digital interactions at do
 main boundaries. Furthermore, verifying complex Unified Power Format (UPF)
  strategies for isolation and retention adds significant complexity. Tradi
 tional full SPICE simulations for comprehensive power state validation are
  prohibitively time-consuming, often requiring weeks of runtime and delayi
 ng time-to-market by months. \n\nTo address these profound limitations, Mi
 crochip, in collaboration with Siemens EDA, developed an optimized mixed-s
 ignal verification methodology for comprehensive SoC power system validati
 on. This innovative approach, leveraging Siemens EDA's AI accelerated Soli
 do Simulation Suite employs a digital-on-top strategy, seamlessly integrat
 ing high-fidelity SPICE views for critical analog modules with high-perfor
 mance digital simulation for the broader RTL design and UPF strategies. \n
 \nIn this presentation, we will detail this novel methodology and demonstr
 ate how it achieves more than 22X runtime reduction for power states simul
 ation without compromising accuracy, thereby enabling rapid and accurate v
 erification of critical power management scenarios. This approach leads to
  improving verification coverage, Silicon quality and accelerating time-to
 -market for robust, energy-efficient SoCs.\n\nTopics: AI, Chiplet, Design,
  EDA, Quantum, Security, Systems\n\n
END:VEVENT
END:VCALENDAR