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DTSTAMP:20260715T200608Z
LOCATION:DAC Pavilion\, Exhibit Floor
DTSTART;TZID=America/Los_Angeles:20260729T150000
DTEND;TZID=America/Los_Angeles:20260729T160000
UID:dac_DAC 2026_sess296_ENGPOST265@linklings.com
SUMMARY:From bottleneck to Breakthrough! Accelerating Circuit Verification
  Beyond Expectations
DESCRIPTION:Kesmat Shahin (Siemens), Monil Patel and Amal Raj (Microsoft),
  and Gaurav Deshpande (Siemens)\n\nModern system-on-chip (SoC) designs fac
 e exponential complexity with billions of geometries and hierarchical inte
 gration. Using traditional layout versus schematic (LVS) verification in e
 arly phases presents significant bottlenecks in complex SoC designs, leadi
 ng to prolonged design cycles and increased costs on the entire verificati
 on flow since shorts are fundamental connectivity flaws that critically im
 pact & bottleneck essential verification flows (e.g., ESD (electrostatic d
 ischarge), LUP (latch-up), Antenna, …etc.). A clean "shorts-free" database
  is a prerequisite for accurate & efficient execution of these flows.\nIn 
 this paper, we are introducing a novel Targeted Short Isolation (SI) verif
 ication methodology designed to transform LVS from a bottleneck into a bre
 akthrough. Our shift-left approach accelerates full verification flow by e
 nabling early detection and remediation of shorts during the Floorplan and
  Place & Route stages. By decoupling targeted SI from full LVS complexity,
  designers can achieve focused remediation without the overhead of compreh
 ensive connectivity checking. Our plug-and-play solution offers remarkable
  improvements, including up to 14X faster iterations and up to 90% memory 
 savings, significantly reducing hardware requirements and improving design
  quality through early detection. Ultimately, this leads to a cleaner, "sh
 ort-free" database across all hierarchies earlier in the design flow, enab
 ling faster time-to-market for complex SoC designs.\n\nTopics: AI, Chiplet
 , Design, EDA, Quantum, Security, Systems\n\n
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