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DTSTAMP:20260730T152728Z
LOCATION:DAC Pavilion\, Exhibit Floor
DTSTART;TZID=America/Los_Angeles:20260729T150000
DTEND;TZID=America/Los_Angeles:20260729T160000
UID:dac_DAC 2026_sess296_ENGPOST261@linklings.com
SUMMARY:Mixed Transistor Design Closure
DESCRIPTION:Ajoy Mandal and Muthu A L (Texas Instruments) and Ravinder Kum
 ar, Alok Verma, and Amit Dhuria (Cadence Design Systems, Inc.)\n\nDesignin
 g circuits with mix of different types transistor to achieve the right bal
 ance between performance and power has been a long used strategy. The semi
 conductor industry has been dealing with variability of transistors and al
 so the extent of miscorrelations between them through skewed corners and d
 erates. Lack of automation to fix these violations led to elongated cyclet
 imes to address them manually. We cover a significant improvement in the p
 revalent methodology. Cadence's Vt skew flow can handle miscorrelations be
 tween transistors efficiently, eliminating overhead of additional STA runs
 . Flow is supported in Innovus and Tempus enabling optimization and timing
  signoff. Solution relies on a creation of bounded GBA which leads to sign
 ificant pessimism in Innovus impacting optimization QoR. Signoff accuracy 
 is not impacted by this as PBA analyzes for this effect accurately by expl
 oring all possible skew combinations depending on the transistor types in 
 path. The optimization challenge is overcome by employing methodology whic
 h performs VT skew analysis both in GBA and PBA modes and derives margin. 
 Finally we present results that indicate that the Vt skew flow is able to 
 identify paths vulnerable to transistor skew and optimize them. We have al
 so benchmarked the analysis accuracy against SPICE\n\nTopics: AI, Chiplet,
  Design, EDA, Quantum, Security, Systems\n\n
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