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DTSTAMP:20260730T152728Z
LOCATION:DAC Pavilion\, Exhibit Floor
DTSTART;TZID=America/Los_Angeles:20260729T150000
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UID:dac_DAC 2026_sess296_ENGPOST254@linklings.com
SUMMARY:A Real-time Metric‑Driven Scorecard for Quantifying and Benchmarki
 ng Physical‑Design Quality and Deployment Progress
DESCRIPTION:Murtaza Tankiwala, Ashishkumar Pal, Kavithaa Rajagopalan, and 
 Ananya Gupta (Texas Instruments)\n\nProblem Statement & Motivation\n\n• Th
 is paper presents an automated scorecard analysis system designed to syste
 matically evaluate and track design quality metrics throughout the develop
 ment cycle. \n• The system provides quantifiable insights into design usin
 g a weighted categorical scoring approach, highlighting optimization oppor
 tunities and flow gaps, enabling project teams to make informed decisions 
 based on severity-categorized metrics. \n• This Scorecard tracker applicat
 ion is designed to manage and display the scores of various physical desig
 n runs to ensure design quality through a structured checklist-based scori
 ng process. This tool presents designers with categorized information to e
 nable pin-pointed evaluation to improve quality while reducing manual effo
 rts, leading to improved turnaround time for design closure.\n• The tool o
 ffers various features such as quality assessment of flow logs, quality ch
 ecks on run environment, highlighting missed checks and ensuring each manu
 al checks is run and cleaned up. This is done along with binning checks in
 to different categories to help designers prioritize debugs. \n• The syste
 m allows users to monitor their runs efficiently. It is built with a focus
  on usability and monitoring various flow of physical design (Synthesis, P
 nR, reliability, CV, custom flows) which are used for the development of S
 OC. \n• Results demonstrate improved prediction of design quality issues a
 nd more effective allocation of engineering resources, leading to measurab
 le reductions in design iterations and validation time while maintaining h
 igh quality during implementation. \n• Additionally, all the scores for ea
 ch run, project and block are logged centrally which helps in analyzing tr
 ends of design closure during and after implementation of design. This can
  be an effective tool to collate learning during implementation and improv
 ing design cycle for up-coming designs.\n\nTopics: AI, Chiplet, Design, ED
 A, Quantum, Security, Systems\n\n
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