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DTSTAMP:20260730T152728Z
LOCATION:DAC Pavilion\, Exhibit Floor
DTSTART;TZID=America/Los_Angeles:20260729T150000
DTEND;TZID=America/Los_Angeles:20260729T160000
UID:dac_DAC 2026_sess296_ENGPOST251@linklings.com
SUMMARY:Hierarchical IP Block Resizing on the Fly
DESCRIPTION:William Dougherty, Eduard Herkel, Alexander Laichinger, Timoth
 y Schell, Julian Stefanac, and Alexander Suess (IBM Research)\n\nTo proof 
 an IC concept early, critical areas of the design are synthesized using a 
 PD synthesis flow.\nIP block data may be incomplete and IP blocks may be a
 dded to a design later. Manually defining physical parameters of IP blocks
  based on functional requirements is an inaccurate and time-consuming step
  during synthesis. To enable synthesis for timing-critical subsets of inco
 mplete IC designs, a novel PD synthesis methodology demonstrates the detec
 tion of any IP blocks of an IC design during synthesis, the scaling of IP 
 blocks to proper sizes, and placing the respective blocks which increases 
 the PD synthesis efficiency by 60%. The system comprises a configuration d
 atabase storing IP block configuration data indexed using block-specific h
 ierarchical identifiers. The method comprises retrieving initial configura
 tion data for IP blocks from the configuration database using the block-sp
 ecific hierarchical identifiers. A recommender system fetches existing IC 
 configuration data and recommends sizes for blocks of the incomplete IC de
 sign. In addition, size changes for IP blocks can be provided to automatic
 ally generate updated IP block configuration data using size changes to mo
 dify the initial IP block configuration. Based on the changes, the configu
 ration database is updated using the new IP block configuration.\n\nTopics
 : AI, Chiplet, Design, EDA, Quantum, Security, Systems\n\n
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