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DTSTAMP:20260730T152726Z
LOCATION:DAC Pavilion\, Exhibit Floor
DTSTART;TZID=America/Los_Angeles:20260729T150000
DTEND;TZID=America/Los_Angeles:20260729T160000
UID:dac_DAC 2026_sess296_ENGPOST243@linklings.com
SUMMARY:Automated Workload Analysis for Dynamic Voltage Drop Optimization 
 and Faster Power Integrity Signoff in Complex SoC Designs
DESCRIPTION:Priyanshu M, Hemanth Karnati, Bhupesh Bakshi, and Mohammed You
 suff Shariff (ARM)\n\nAs power integrity margins continue to tighten in ad
 vanced nodes and 3DIC designs, identifying the true worst-case PDN stress 
 scenarios across multiple compute tiles has become increasingly complex an
 d time-consuming. Traditional manual exploration of block workloads and ve
 ctor combinations often requires expert intervention, exhaustive simulatio
 ns, and significant runtime. To address this challenge, we present an auto
 mated RedHawk-SC framework that intelligently explores Reduced Order Model
 s(ROM)-based block workload combinations to uncover high-stress PDN condit
 ions with minimal runtime overhead.\n\nThe proposed flow introduces a nove
 l scenario optimization algorithm that automatically generates, ranks, and
  prunes workload mixes for each compute tile, capturing die-package co-ana
 lysis through integrated RedHawk-SC simulations. The framework incorporate
 s workload intelligence to learn per-block power impact, adaptive optimiza
 tion to select optimal workload pairings using a greedy exploration algori
 thm, and scalability across multiple domains and workload vectors. Impleme
 nted as a Python wrapper, it delivers a plug-and-play architecture support
 ing automation and rapid integration within existing analysis environments
 .\n\nThis automated flow replaces expert-driven manual analysis with a dat
 a-guided methodology that ensures accurate prediction of voltage stress re
 gions, early detection of grid vulnerabilities, and stronger silicon corre
 lation. The approach simplifies scenario complexity, enhances reliability 
 coverage, and accelerates sign-off for chiplet and 3DIC architectures.\n\n
 Topics: AI, Chiplet, Design, EDA, Quantum, Security, Systems\n\n
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