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BEGIN:VEVENT
DTSTAMP:20260730T152728Z
LOCATION:DAC Pavilion\, Exhibit Floor
DTSTART;TZID=America/Los_Angeles:20260729T150000
DTEND;TZID=America/Los_Angeles:20260729T160000
UID:dac_DAC 2026_sess296_ENGPOST240@linklings.com
SUMMARY:Scalable EMIR Signoff for Very Large SoCs using Reduced Order Mode
 lling
DESCRIPTION:Priyanshu M, Hemanth Karnati, Bhupesh Bakshi, and Mohammed You
 suff Shariff (ARM)\n\nAt advanced process nodes, flat EMIR signoff for mod
 ern SoCs often exceeding four billion instances and 50 billion nodes faces
  prohibitive runtime and compute demands. This work introduces a productio
 n-proven hierarchical EMIR signoff methodology leveraging Reduced Order Mo
 del (ROM) technology to achieve scalable, resource-efficient IR/EM analysi
 s for billion-instance systems. The proposed bottom-up flow generates comp
 act ROMs that preserve electrical and geometric characteristics of child b
 locks across defined Common Connection Layers (CCL), enabling accurate hie
 rarchical modeling without full flat complexity. Integrated automation ens
 ures consistent ROM generation, validation, and consumption across multi-s
 cenario, multi-PVT signoff environments. The resulting hierarchical analys
 is achieves near-flat accuracy with over 50% reduction in runtime and memo
 ry footprint, supporting realistic workload and packaging variations. Vali
 dation on the large scale SoC demonstrates around 75% total compute-hour r
 eduction, 55% disk space savings and 35% memory improvement. \nThis method
 ology has been successfully deployed in production for next-generation Arm
  SoCs, enabling faster turnaround and efficient compute utilization in bot
 h on-premise and hybrid cloud environments. The flow establishes a scalabl
 e, practical, and high-fidelity EMIR signoff paradigm transforming hierarc
 hical verification for large-scale, advanced-node SoCs.\n\nTopics: AI, Chi
 plet, Design, EDA, Quantum, Security, Systems\n\n
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