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BEGIN:VEVENT
DTSTAMP:20260730T152728Z
LOCATION:DAC Pavilion\, Exhibit Floor
DTSTART;TZID=America/Los_Angeles:20260729T150000
DTEND;TZID=America/Los_Angeles:20260729T160000
UID:dac_DAC 2026_sess296_ENGPOST227@linklings.com
SUMMARY:Tackling Local Noise Coverage Limitations in Transient EMIR Analys
 is for Robust SoC-level PDN Closure
DESCRIPTION:Akhilesh Mishra, Abhinav Gaur, and MANOJ CHAHANDE (NXP) and Am
 it Jangra, Shreyashi ., and Shatakshi Srivastava (Synopsys)\n\nThe methods
  traditionally used to analyse dynamic voltage drop on complex automotive 
 SoCs are becoming increasingly inadequate in identifying important local s
 imultaneous switching noise conditions that affect timing. Designers face 
 significant challenges in EMIR signoff for such SoCs.\n\nCoverage is sever
 ely limited for local switching noise, as most voltage drops arise from ag
 gressors activity around a victim cell and significantly very less from ce
 ll's self-switching. Transient EMIR analysis is very sensitive to simulati
 on timestep which should be small 5-10ps to ensure accuracy, limiting runt
 ime for higher local noise coverage. For VCD-based flows, it is practicall
 y impossible to get proper vectors for 100% IR-drop coverage.\n\nTo overco
 me the above local noise coverage limitations in traditional EMIR, we pres
 ent here a novel aggressor-coverage based sigma methodology that calculate
 s realistic dynamic IR on all instances by taking a collection of all poss
 ible aggressors to each victim instance. It provides debug visibility to t
 he designers to enable fixing violations early. Our methodology helps both
  in runtime reduction as well as uncovering IR hotspots missed in traditio
 nal approach to improve PDN robustness. Our results show high local noise 
 coverage along with 2X runtime improvements that can be efficiently used t
 o signoff EMIR with high confidence.\n\nTopics: AI, Chiplet, Design, EDA, 
 Quantum, Security, Systems\n\n
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