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DTSTAMP:20260730T152727Z
LOCATION:DAC Pavilion\, Exhibit Floor
DTSTART;TZID=America/Los_Angeles:20260729T150000
DTEND;TZID=America/Los_Angeles:20260729T160000
UID:dac_DAC 2026_sess296_ENGPOST213@linklings.com
SUMMARY:Revisiting PDN at the MOL Boundary: A Placement-Aware Power Delive
 ry Flow
DESCRIPTION:Insub Shin, Joonyoung Shin, Myeonggyun Jeong, Sangdo Park, Jun
  Seomun, and Hyung-Ock Kim (Samsung Electronics)\n\nAt advancded nodes, ag
 gressive cell height scaling has made lower metal routing resources a prim
 ary limiter for block-level PPA, as these layers are simultaneously demand
 ed by signal routing, pin access, and power delivery. While adding more ro
 uting layers can increase overall capacity, the benefit diminishes with de
 eper metal stacks, leaving lower metals as the most performance-critical a
 nd congested resources.\n\nThis work revisits power delivery at the middle
 -of-line (MOL) boundary and proposes a placement-aware MOL-PDN integration
  flow that redistributes PDN burden away from lower metals without alterin
 g the conventional P&R flow. The proposed approach introduces MOL-level PD
 N segments during pre-placement and further adapts them after routing, ena
 bling effective lower-metal resource reallocation while preserving the con
 ventional physical design methdology.\n\nExperiments on a large ARM CPU su
 b-block show that the proposed MOL-PDN flow achieves up to 0.6% frequency 
 improvement and up to 1.5% total wirelength reduction compared to a conven
 tional lower-metal PDN scheme. Static IR behavior is maintained, while inc
 reased dynamic IR sensitivity is observed under signoff worst-case conditi
 ons.\n\nTopics: AI, Chiplet, Design, EDA, Quantum, Security, Systems\n\n
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