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DTSTAMP:20260730T152727Z
LOCATION:DAC Pavilion\, Exhibit Floor
DTSTART;TZID=America/Los_Angeles:20260729T150000
DTEND;TZID=America/Los_Angeles:20260729T160000
UID:dac_DAC 2026_sess296_ENGPOST209@linklings.com
SUMMARY:ECO Strategy for BIG DIE SOC Convergence
DESCRIPTION:Sabya Sachi Sahu, Aniket Agrawal, and Pushpendra Yadav (Samsun
 g Electronics) and Raghu M S and Chetan B S (Cadence Design Systems, Inc.)
 \n\nThe SSIR Customer Design Service (CDS) team supports projects spanning
  big die AI, automotive, and HPC SoCs. Schedules and designs demand static
  timing analysis (STA) and engineering change order (ECO) flows that close
  designs quickly. An ECO strategy for a large die AI SoC is difficult: the
  design contains about 1.6 billion instances, must meet a 1.6 GHz target, 
 and relies heavily on multiply-instantiated-modules (MIM). MIMs complicate
  violation fixes because each change must be evaluated for impact on other
  MIMs. Additional challenges include clock path skew, extensive boundary m
 odels (BMs), and long data paths, all hindering a sustainable ECO methodol
 ogy.\n\nTo address these issues, the team adopted a "divide and conquer" p
 olicy. Multiple STA models with BMs were generated for the top level, enab
 ling parallel analysis and reducing compute load and turnaround time. The 
 CERTUS platform, with its advanced high capacity (HC) ECO engine, prunes t
 he netlist by identifying violations, making the flow lightweight and effi
 cient. At the block level, Twopass and Paradigm were used as ECO tools to 
 converge the design. SSIR worked closely with Cadence field and R&D groups
  to tailor the flow, creating a recipe that significantly improves fix rat
 es while preserving timing, logical DRCs, and legalization.\n\nTopics: AI,
  Chiplet, Design, EDA, Quantum, Security, Systems\n\n
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