BEGIN:VCALENDAR VERSION:2.0 PRODID:Linklings LLC BEGIN:VTIMEZONE TZID:America/Los_Angeles X-LIC-LOCATION:America/Los_Angeles BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:19700308T020000 RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:19701101T020000 RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20260730T152639Z LOCATION:DAC Pavilion\, Exhibit Floor DTSTART;TZID=America/Los_Angeles:20260728T170000 DTEND;TZID=America/Los_Angeles:20260728T180000 UID:dac_DAC 2026_sess295_ENGPRES441@linklings.com SUMMARY:Weeding Out Timing Gaps and Improving Performance of DDR Controlle rs Using Formal Verification DESCRIPTION:Raushan Kumar and Anshul Jain (Synopsys)\n\nLPDDR6 delivers su bstantial gains in bandwidth, power efficiency, and scalability through ph ase‑aware command scheduling, multi‑sub‑channel architectures, and data ra tes reaching 12.8 GT/s. These architectural innovations significantly comp licate the verification of minimum timing constraints and performance‑crit ical behaviours in memory controllers, where simulation‑based approaches f ail to expose phase‑dependent corner cases and sub‑optimal scheduling inte ractions.\nThis paper presents a scalable Formal Property Verification (FP V) framework to exhaustively validate LPDDR6 timing correctness and system atically analyze controller‑level performance limitations. The approach em ploys a generic timing reference model augmented with frequency‑mode‑aware phase counters, constrained timing registers, and state‑driven SystemVeri log Assertions (SVA) to precisely track command scheduling across 1:2:4 an d 1:4:8 clocking modes. The formal methodology detects minimum‑timing cons traint violations and LPDDR6 performance degradation, ensuring strict mini mum‑timing compliance while improving memory‑controller scheduling efficie ncy.\nApplied across all 16 LPDDR6 supported data rates, the framework unc overed multiple timing and performance defects, improved scheduling robust ness, and enabled early detection of corner‑case issues. These results dem onstrate that FPV is an effective and scalable solution for ensuring LPDDR 6 timing compliance while maximizing memory‑controller performance.\n\nTop ics: AI, Chiplet, Design, EDA, Quantum, Security, Systems\n\n END:VEVENT END:VCALENDAR