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DTSTAMP:20260730T152639Z
LOCATION:DAC Pavilion\, Exhibit Floor
DTSTART;TZID=America/Los_Angeles:20260728T170000
DTEND;TZID=America/Los_Angeles:20260728T180000
UID:dac_DAC 2026_sess295_ENGPRES423@linklings.com
SUMMARY:Modeling and Optimization of Power MOSFET Device Layouts with opti
 SLang Tool
DESCRIPTION:Mandar Deshpande and Claudia Dumitrescu (Microchip) and Khawja
  Sikander (Synopsys)\n\nThe performance of large semiconductor devices, su
 ch as power MOSFETS that carry large currents, depends not only on their s
 ize or area but also their layout and package implementation choices. Fact
 ors such as device aspect ratios, metal routing strategies and pad locatio
 ns influence current flow through the device and impact device characteris
 tics such as its on resistance (Rdson) and reliability. \n\nIt has been ch
 allenging to model these layout and configuration dependent effects. Optim
 izing the device layouts and pad configurations has been a manually iterat
 ive and time-consuming task, often done towards the end of the design cycl
 e, resulting in increased risk of sub-optimal designs. \n\nWe propose a ne
 w methodology utilizing the features available in Ansys (now Synopsys) opt
 iSLang tool to address this problem. We demonstrate a novel flow which int
 egrates Cadence Virtuoso p-cell/skill scripts for device layout generation
  with Ansys Totem tool with PMIC utility for layout extraction and analysi
 s. We utilize in-built optiSLang algorithms to run sensitivity analysis an
 d develop meta-models. We envision a flow where process technology or PDK 
 development teams will generate a device meta-model early on which can be 
 exported as a python function. Design or packaging teams can use the simpl
 e function to identify and implement optimally sized devices as per their 
 product requirements.  \nWe will present a couple of examples to describe 
 the optiSLang based flows and present power MOSFET device modeling and opt
 imization results.\n\nTopics: AI, Chiplet, Design, EDA, Quantum, Security,
  Systems\n\n
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