BEGIN:VCALENDAR VERSION:2.0 PRODID:Linklings LLC BEGIN:VTIMEZONE TZID:America/Los_Angeles X-LIC-LOCATION:America/Los_Angeles BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:19700308T020000 RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:19701101T020000 RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20260730T152639Z LOCATION:DAC Pavilion\, Exhibit Floor DTSTART;TZID=America/Los_Angeles:20260728T170000 DTEND;TZID=America/Los_Angeles:20260728T180000 UID:dac_DAC 2026_sess295_ENGPRES422@linklings.com SUMMARY:BIMEM-RAG: Reinforced Dual Memory Retrieval with Bidirectional Rea soning for RTL Synthesis and Summarization DESCRIPTION:Prashanth Vijayaraghavan, Luyao Shi, Apoorva Nitsure, David Be ymer, Ehsan Degan, and Vandana Mukherjee (IBM Research)\n\nAutomating Regi ster-Transfer Level (RTL) code generation and summarization is critical fo r improving hardware design productivity and reducing time-to-market. Howe ver, existing approaches struggle due to limited Verilog and VHDL training data and the structural concurrency inherent in hardware description lang uages (HDLs). We propose BiMem-RAG, a dual-memory retrieval and bidirectio nal reasoning framework for HDL synthesis and documentation. BiMem-RAG com bines (i) an exemplar memory of specification-to-code and code-to-summary pairs indexed using joint code and abstract syntax tree embeddings, and (i i) an analogical memory capturing reusable hardware design patterns such a s sequential and combinational logic. The system employs modular decomposi tion, reinforcement-guided retrieval, and backward verification to improve semantic fidelity and reduce hallucinations. Experiments on Verilog and V HDL benchmarks demonstrate up to 19 percentage-point improvements in Pass@ 1 and 9-point gains in ROUGE-L over strong baselines. These results show t hat structured retrieval and verification significantly improve RTL genera tion and summarization, enabling more reliable hardware design automation. \n\nTopics: AI, Chiplet, Design, EDA, Quantum, Security, Systems\n\n END:VEVENT END:VCALENDAR