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DTSTAMP:20260730T152639Z
LOCATION:DAC Pavilion\, Exhibit Floor
DTSTART;TZID=America/Los_Angeles:20260728T170000
DTEND;TZID=America/Los_Angeles:20260728T180000
UID:dac_DAC 2026_sess295_ENGPRES346@linklings.com
SUMMARY:Graph Isomorphism for Explainable Transistor-level Circuit Compari
 son
DESCRIPTION:Ashutosh Jadhav, Xin Zhao, Ehsan Degan, and Vandana Mukherjee 
 (IBM Research)\n\nCircuit comparison is a fundamental task to determine wh
 ether two circuit representations are structurally and electrically equiva
 lent. Modern EDA flows frequently introduce renaming, reordering, and symm
 etry-preserving transformations even when functionality is unchanged. Exis
 ting pattern-matching approaches typically focus on exact topological matc
 hes and return a binary match or no-match result, providing little insight
  into the cause of the mismatch. Consequently, engineers must perform manu
 al, time-consuming root-cause analysis, slowing verification cycles and in
 creasing development cost.\n\nThis work presents a graph-isomorphism–based
  framework for explainable transistor-level circuit comparison. Each circu
 it is modeled as a labeled graph in which nodes encode device and net sema
 ntics (PFET/NFET, supply classification, externality) and edges encode tra
 nsistor terminal roles (gate/drain/source). Structural correspondence is c
 omputed using the VF2 graph isomorphism algorithm, independent of naming. 
 Candidate mappings are validated using semantics-aware electrical rules th
 at preserve gate connectivity, allow drain–source symmetry, and enforce su
 pply and external/internal net constraints. The framework classifies diffe
 rences into meaningful categories, including exact matches, accepted conne
 ct mismatches, label mismatches, and missing or extra elements. The propos
 ed approach enables precise circuit comparison for LVS-style verification,
  ECO intent validation, and IP-version diffing, significantly reducing fal
 se mismatches and manual debug effort while reliably identifying true stru
 ctural and electrical changes.\n\nTopics: AI, Chiplet, Design, EDA, Quantu
 m, Security, Systems\n\n
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