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BEGIN:VEVENT
DTSTAMP:20260730T152639Z
LOCATION:DAC Pavilion\, Exhibit Floor
DTSTART;TZID=America/Los_Angeles:20260728T170000
DTEND;TZID=America/Los_Angeles:20260728T180000
UID:dac_DAC 2026_sess295_ENGPRES333@linklings.com
SUMMARY:A Programmable, Synthesizable CMOS Analog Optimization IP Core for
  Real-Time Control
DESCRIPTION:Priyanshu Sahu, Swapnil Sharma, Sachin Khoja, and Palak Jain (
 Vellex Computing) and Jason Poon (Cal Poly, San Luis Obispo)\n\nThis work 
 presents an automated EDA toolchain for synthesizing programmable and scal
 able CMOS analog optimization IP cores. Addressing the latency wall in rea
 l-time control, where conventional digital solvers face polynomial scaling
  bottlenecks, our methodology translates high-level mathematical specifica
 tions (AMPL/MPS) directly into verification-ready SPICE netlists. The synt
 hesized IP utilizes a reconfigurable switched-capacitor architecture that 
 implements continuous-time Karush-Kuhn-Tucker dynamics, allowing it to sol
 ve constrained optimization problems through parallel physics-based evolut
 ion rather than sequential algorithms.Unlike prior art limited to small-sc
 ale fixed-function circuits, our architecture incorporates a software-driv
 en calibration layer to neutralize PVT variations, ensuring reliability in
  standard CMOS nodes. We demonstrate the flow's scalability on problem siz
 es ranging from dense 500-variable instances to sparse 10,000-variable wor
 kloads. Results show the generated IP achieves invariant sub-millisecond c
 onvergence regardless of complexity, delivering a >300X speedup over state
 -of-the-art digital interior-point solvers while maintaining solution accu
 racy within 0.02% relative error. This work provides a complete code-to-si
 licon path for deploying high-performance analog computing in edge AI and 
 real-time control systems.\n\nTopics: AI, Chiplet, Design, EDA, Quantum, S
 ecurity, Systems\n\n
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