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DTSTAMP:20260730T152639Z
LOCATION:DAC Pavilion\, Exhibit Floor
DTSTART;TZID=America/Los_Angeles:20260728T170000
DTEND;TZID=America/Los_Angeles:20260728T180000
UID:dac_DAC 2026_sess295_ENGPRES259@linklings.com
SUMMARY:Deep Reinforcement Learning Paradigm for Analog Design Automation
DESCRIPTION:Sharath C R, Senthil Kumar Sundaramoorthy, Krishna Teja, Chana
 kya K V, Sujith M A, and Suberus Heartrisha (Texas Instruments)\n\nWe prop
 ose a tool capable of Automating Analog Design Sizing at scale in an indus
 trial setting that meets sign-off quality. There have been several academi
 c papers which talk about optimizing analog circuit but most of them opera
 te under the academic umbrella which prohibits them from being viable solu
 tions in the industrial setting where there are complex device models, PVT
  and Mismatch (MC) simulations, complex topologies with large number of de
 sign variable and specifications that have to be met with certain priority
 .\n\nThe proposed tool addresses all these challenges and is proven within
  our company to be a "Real" Analog Design Optimization tool.\n\nWe use Dee
 p Reinforcement Learning and unique reward shaping algorithms to optimally
  tune device parameters to meet design specifications provided by the desi
 gners. The tool optimizes the design across all PVT (Process, Voltage, Tem
 perature) corners and Mismatch (Monte Carlo) corners to produce a optimize
 d circuit that is indistinguishable from a manually fine tuned circuit exp
 ect for the fact that, it does this much faster and arrives at the best po
 ssible solution (at least as good as the designer). It does this within a 
 practical timeframe while being computationally economical.\n\nAt TI the s
 olution is widely deployed and, 100+ analog circuits/blocks have been opti
 mized with the proposed solution.\n\nTopics: AI, Chiplet, Design, EDA, Qua
 ntum, Security, Systems\n\n
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