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BEGIN:VEVENT
DTSTAMP:20260730T152639Z
LOCATION:DAC Pavilion\, Exhibit Floor
DTSTART;TZID=America/Los_Angeles:20260728T170000
DTEND;TZID=America/Los_Angeles:20260728T180000
UID:dac_DAC 2026_sess295_ENGPRES222@linklings.com
SUMMARY:A Distributed and Scalable Dynamic Power Integrity Flow from Early
  Analysis to Sign-off for Large-Scale SerDes Designs
DESCRIPTION:Xin Shu, Jinrong Yan, Hang Sun, Xuewei Ding, and Xiaofan Lu (S
 anechips Technology Co.,Ltd) and Xiaomei You and Jie Cheng (Synopsys)\n\nF
 or large-scale SerDes designs, dynamic power integrity sign-off is becomin
 g increasingly challenging due to growing design scale and performance dem
 ands. Modern SerDes integrate analog blocks, digital blocks, sensitive clo
 cks, decaps with complex Power Delivery Network (PDN) design. Such designs
  can reach tens of millions of transistors and multi-million-node as desig
 n nodes shrinking, making full-chip dynamic EMIR sign-off and Chip Power M
 odel (CPM) generation difficult. In addition, data rates are scaling from 
 56G to 112G and 224G, leading to higher switching activity and larger tran
 sient current peaks. Accurate sign-off and CPM generation require smaller,
  picosecond-level time resolution and long transient windows of up to hund
 reds of nanoseconds, making sign-off runtime even longer.\nIn traditional 
 power integrity analysis, existing EMIR tools have limited distributed sca
 lability for full-chip, multi-domain SerDes designs. Realistic dynamic sim
 ulations often exhibit low parallel efficiency and inefficient utilization
  of computing resources, resulting in long runtime to days or even weeks. 
 To reduce runtime and resource usage, designers have to downsize current v
 ector capture window or simplify extracted networks, which impacts overall
  power integrity analysis accuracy. Moreover, past early analysis is typic
 ally limited to simple static analysis, while dynamic analysis and CPM gen
 eration can only be performed at the sign-off stage, making chip-package-s
 ystem PDN co-optimization hard to process in early stage.\nHere, we adopt 
 a distributed and scalable dynamic power integrity flow from early analysi
 s to sign-off. Early-stage dynamic power integrity analysis based on Build
  Quality Metric (BQM) provides early EMIR insight and enables early CPM ge
 neration for package- and system-level power integrity analysis, allowing 
 issues to be addressed earlier and reducing sign-off iterations. Distribut
 ed and scalable dynamic EMIR sign-off flow enables efficient full-chip ana
 lysis under realistic workloads through multi-machine, multi-thread parall
 elism, without simplifying extracted networks or reducing analysis windows
 . With the unified dynamic power integrity flow from early analysis to sig
 n-off, analysis efficiency is significantly improved while maintaining acc
 uracy and increasing confidence in SerDes design robustness.\nkeywords：lar
 ge-scale Serdes designs, distributed and scalable, dynamic power integrity
 , Chip Power Model\n\nTopics: AI, Chiplet, Design, EDA, Quantum, Security,
  Systems\n\n
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