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BEGIN:VEVENT
DTSTAMP:20260730T152639Z
LOCATION:DAC Pavilion\, Exhibit Floor
DTSTART;TZID=America/Los_Angeles:20260728T170000
DTEND;TZID=America/Los_Angeles:20260728T180000
UID:dac_DAC 2026_sess295_ENGPRES156@linklings.com
SUMMARY:Correct-by-Construction Framework for Robustness Against Divergent
  Voltage Drops and High Clock Divergence
DESCRIPTION:PRATEEK PENDYALA and Mathew Kaipanatu (Google)\n\nLimitations 
 in Sign-off Methodology:\nTraditional STA corner selection 10% lower STA c
 orner from PMIC voltage is selected-  design is constantly optimised for 1
 0% lower voltage, thereby failing to build margin against differential dro
 p.\nIR aware STA does not account timing path's geometric imbalances (logi
 c depths), net dominated interconnect skews (net delays & metal layer vari
 ation) - all dominant in advanced process nodes. Furthermore, this is work
 load dependent: fixing IR STA violations does not build margins on unseen 
 vectors.\nFrequent Silicon issues due to these gaps:\nLow voltage mode sca
 n shift Vmin jumps need to meet slack on paths which become exponentially 
 sensitive to voltage gradients. Even small differential IR drops (capture 
 & launch traversing through contrasting IR hotspot & cool regions) cause c
 atastrophic slack loss\nHigh divergence paths with structural imbalances-w
 here clock paths are net-dominated & are operated at high speeds often fai
 l to meet hold timing, despite good pre-silicon margins due to high interl
 ayer metal-sheet & via resistances in lower process nodes.\nAdditionally, 
 there is considerable PPA impact -higher dynamic & leakage power in clock 
 & data paths respectively in divergent paths. Our proposed solution aims t
 o address above gaps.\n\nTopics: AI, Chiplet, Design, EDA, Quantum, Securi
 ty, Systems\n\n
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