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DTSTAMP:20260730T152639Z
LOCATION:DAC Pavilion\, Exhibit Floor
DTSTART;TZID=America/Los_Angeles:20260728T170000
DTEND;TZID=America/Los_Angeles:20260728T180000
UID:dac_DAC 2026_sess295_ENGPRES140@linklings.com
SUMMARY:Multi-Agent Generative AI Pipeline for assisting in Design Verific
 ation
DESCRIPTION:Pratham Gowtham, Tejas Bhat, Chethan Bomanna, and Anil Deshpan
 de (Samsung Electronics)\n\nSecure Multi-Agent Generative AI Pipeline for 
 Context-Aware Design Verification\n\nThe escalating complexity of modern S
 ystem-on-Chip (SoC) designs has relegated approximately 70% of the total d
 esign cycle to functional verification. This critical phase is currently p
 lagued by knowledge fragmentation, where engineers lose significant time m
 anually parsing massive technical specifications (JEDEC, LPDDR, HBM), and 
 the repetitive overhead of writing boilerplate UVM code and assertions. Wh
 ile Large Language Models (LLMs) offer a potential solution, public AI ser
 vices present an unacceptable security risk for the leakage of proprietary
  RTL and confidential company data.\n\nThis presentation puts forth a nove
 l, on-premise agentic AI pipeline designed to automate the verification li
 fecycle within a secure local environment. Our architecture utilizes a "Te
 am of Experts" approach orchestrated by a central Classifier Agent that ro
 utes complex queries to specialized sub-agents for code generation, log pa
 rsing, and spec retrieval. By leveraging Retrieval-Augmented Generation (R
 AG) and decoupled fine-tuning, the system provides high-fidelity, context-
 aware assistance tailored to internal design methodologies without risking
  external data exposure. This modular framework significantly enhances eng
 ineering productivity, reduces time-to-market (TTM), and ensures the secur
 ity of sensitive silicon IP.\n\nTopics: AI, Chiplet, Design, EDA, Quantum,
  Security, Systems\n\n
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