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DTSTAMP:20260730T152639Z
LOCATION:DAC Pavilion\, Exhibit Floor
DTSTART;TZID=America/Los_Angeles:20260728T170000
DTEND;TZID=America/Los_Angeles:20260728T180000
UID:dac_DAC 2026_sess295_ENGPRES065@linklings.com
SUMMARY:Accelerating Formal Closure on Complex Hardware Designs via AI-Dri
 ven Helper Generation
DESCRIPTION:Bindumadhava Singanamalli and Pandithurai Sangaiyah (Google) a
 nd Sean Safarpour, Sayandeep Sayandeep Sanyal, Sandeep Jana, and Raja Maha
 devan (Synopsys)\n\nAs hardware designs grow in complexity, Formal Verific
 ation (FV) often hits scalability walls, resulting in "bounded" proofs rat
 her than full closure.Deep state-space exploration is limited by computati
 onal resources. Overcoming this typically requires "helper" assertions (in
 variants), but manually identifying and writing these is labor-intensive a
 nd requires deep micro-architectural knowledge. In this presentation, we p
 resent our findings where we used AI/ML & GenFV to generate helpers to ach
 ieve full proofs and reduce the verification cycle time\n\nTopics: AI, Chi
 plet, Design, EDA, Quantum, Security, Systems\n\n
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