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DTSTAMP:20260730T152639Z
LOCATION:DAC Pavilion\, Exhibit Floor
DTSTART;TZID=America/Los_Angeles:20260728T170000
DTEND;TZID=America/Los_Angeles:20260728T180000
UID:dac_DAC 2026_sess295_ENGPRES064@linklings.com
SUMMARY:Automating DFT Intelligence: Addressing TCPF HotSpots at Source th
 rough Design Aware Test Points in SystemRDL-to-RTL Generators
DESCRIPTION:Veerabhadrarao Vasa and Rajesh Gottumukkala (Google) and Vikas
 h Gupta and Freddy Nunez (Agnisys)\n\nAs SoC complexity scales, the result
 ing explosion in Automatic Test Pattern Generation (ATPG) pattern counts h
 as become a primary driver of escalating manufacturing test costs. A criti
 cal bottleneck in this process is the emergence of "TCPF (Test cost Per Fa
 ult) Hotspots" across designs such as highly complex, auto-generated block
 s such as Control and Status Registers (CSRs) that exhibit disproportionat
 ely high pattern counts due to deep combinational logic and structural bot
 tlenecks like shared address buses. Traditional structural test point inse
 rtion often fails to address these architectural constraints effectively, 
 as it operates on a late-stage netlist without design-specific context.\n\
 nThis paper proposes an "Extreme Left-Shift" methodology that moves DFT in
 telligence directly into the specification-to-RTL generation phase. By int
 egrating Design-Aware Test Points (DATP) natively within a SystemRDL-to-RT
 L generator, we introduce architectural enhancements—including address par
 allelism, local protocol control, and optimized OR-reduction logic—that ar
 e structurally impossible to implement efficiently at the netlist level. T
 his automated approach utilizes intelligent algorithms to analyze input RD
 L specifications and fine-tune DATP parameters at scale.\n\nWe demonstrate
  the efficacy of this methodology on a production-grade Tensor SoC. Experi
 mental results show that while maintaining a minimal area overhead (~0.1%)
 , the proposed DATP solution achieves a 4x improvement in TCPF at the IP l
 evel and a 50% overall reduction in ATPG pattern count at the top level co
 mpared to reference designs. By solving DFT bottlenecks at the source, thi
 s scalable framework provides a robust path for significantly reducing SoC
  test costs across the industry\n\nTopics: AI, Chiplet, Design, EDA, Quant
 um, Security, Systems\n\n
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