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BEGIN:VEVENT
DTSTAMP:20260730T152639Z
LOCATION:DAC Pavilion\, Exhibit Floor
DTSTART;TZID=America/Los_Angeles:20260728T170000
DTEND;TZID=America/Los_Angeles:20260728T180000
UID:dac_DAC 2026_sess295_ENGPOST479@linklings.com
SUMMARY:A Hybrid SRAM-DRAM Memory Architecture for Ultra-Low-Power Wakeup 
 in SoCs
DESCRIPTION:Prasad Dandra (Samsung Electronics); Thejeswara Reddy (Samsung
 ); Tushar Vrind and Somraj Mani (Samsung Electronics); and Venkata Raju In
 dukuri, Krishnakant Patil, and Amol Kumar Jagtap (Samsung)\n\nPower consum
 ption plays a key factor in SoC. With advances made in wireless technologi
 es through 3GPP LTE & NR, IEEE Wifi and now with 3GPP 6G, there is a need 
 for advanced architecture in SoC. Typically, a SoC uses sleep and wakeup (
 warmboot) procedure for saving battery. The warmboot procedure involves ch
 anging DRAM from refresh mode to active mode. This takes certain time unti
 l which other operations get delayed. Also usage of DRAM further consumes 
 power. Hence, hardware design that enables software to have systematic con
 trol on wakeup (warmboot) and sleep operations is required. This idea disc
 usses on design of SoC to use hybrid mode of SRAM and DRAM. SRAM and DRAM 
 are memory entities which play a key role in wakeup, software execution an
 d sleep. With combination of software control on proposed hardware design 
 for system-on-chip, can efficiently increase sleep time by minimizing DRAM
  usage and wakeup time by managing with SRAM along with faster execution o
 f procedures required during wakeup.\n\nTopics: AI, Chiplet, Design, EDA, 
 Quantum, Security, Systems\n\n
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