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DTSTAMP:20260730T152639Z
LOCATION:DAC Pavilion\, Exhibit Floor
DTSTART;TZID=America/Los_Angeles:20260728T170000
DTEND;TZID=America/Los_Angeles:20260728T180000
UID:dac_DAC 2026_sess295_ENGPOST473@linklings.com
SUMMARY:LLM-Aided Cell Clustering for Placement Optimization of DRAM Perip
 heral Circuits
DESCRIPTION:Soyoon Choi, Chansol Hong, Jinyoung Lee, and Hyojin Choi (Sams
 ung Electronics)\n\nPlacement quality strongly impacts routability and tim
 ing in DRAM peripheral circuits. While expert designers manually identify 
 structural patterns of cells to be clustered during placement in small sca
 le circuits to enhance the quality of results (QoR), this approach does no
 t scale to large DRAM peripheral designs.\nThis research proposes an autom
 ated cell clustering method using large language models (LLMs) for DRAM pe
 ripheral circuit placement. Expert knowledge describing the target structu
 ral patterns for clustering is written as natural language prompts. These 
 prompts enable the LLM to interpret the netlist as a graph and identify th
 e target structural patterns. The identified clusters are treated as singl
 e placement instances to achieve structure-aware placement. The proposed a
 pproach allows flexible detection of target structures and remains robust 
 to structural variations without explicit rule-based programming.\nExperim
 ental results on a DRAM peripheral circuit demonstrate a 80.6% reduction i
 n the number of DRVs. Setup WNS improves by 0.9% while hold WNS degrades b
 y 128%, highlighting the importance of timing-aware clustering as future w
 ork.\n\nTopics: AI, Chiplet, Design, EDA, Quantum, Security, Systems\n\n
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