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DTSTAMP:20260730T152639Z
LOCATION:DAC Pavilion\, Exhibit Floor
DTSTART;TZID=America/Los_Angeles:20260728T170000
DTEND;TZID=America/Los_Angeles:20260728T180000
UID:dac_DAC 2026_sess295_ENGPOST471@linklings.com
SUMMARY:Sigma Profiling: Profiling Solution for Power Integrity Signoff
DESCRIPTION:Girish Deshpande, Anusha Vemuri, Vishal Malik, Emmanuel Chao, 
 and Santosh Santosh (NVIDIA) and Chidambaram Rakkappan, Ayush Sood, and Ta
 pas Govindraju (Synopsys)\n\nSigma Profiling offers a breakthrough power i
 ntegrity signoff solution in chip design, overcoming coverage and runtime 
 limitations present in traditional dynamic IR analysis techniques. Convent
 ional methods, such as peak power or tile-based cycle selection, often fai
 l to comprehensively capture high-risk instances due to their reliance on 
 spatial or time averages, frequently missing critical timing paths and loc
 alized IR-drop hotspots. Sigma Profiling addresses these challenges by lev
 eraging instance-level analysis with SigmaDvD technology, which efficientl
 y evaluates aggressor-victim interactions and local voltage drop risks acr
 oss long test vectors.\nThis advanced approach partitions long stimulus ve
 ctors into user-defined slices and calculates instance-level metrics—inclu
 ding logic activity and sigma-based voltage drop. A robust coverage scorin
 g mechanism is then used to pinpoint and prioritize high-impact cycles and
  instances, enabling highly targeted dynamic analysis. As a result, Sigma 
 Profiling delivers maximum coverage of critical and high-risk design regio
 ns, delivering more accurate and actionable signoff feedback.\nBy combinin
 g granular, high-coverage profiling with critical path information, Sigma 
 Profiling facilitates comprehensive detection of major IR-drop hotspots an
 d timing violations. This methodology ensures reliable, efficient power in
 tegrity verification for increasingly complex semiconductor devices.\n\nTo
 pics: AI, Chiplet, Design, EDA, Quantum, Security, Systems\n\n
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