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DTSTAMP:20260730T152728Z
LOCATION:DAC Pavilion\, Exhibit Floor
DTSTART;TZID=America/Los_Angeles:20260728T170000
DTEND;TZID=America/Los_Angeles:20260728T180000
UID:dac_DAC 2026_sess295_ENGPOST276@linklings.com
SUMMARY:An Optimized Full-Chip Analog Mixed-Signal (AMS) Verification Appr
 oach for PVT Calibration in FPGA Systems
DESCRIPTION:Shubhi Agrawal, Ramteja Kothamasu, and Prajjwal Soni (Microchi
 p) and Neel Natekar and Harshit Arora (Siemens)\n\nMicrochip FPGAs feature
  multiple I/O banks, each configurable independently for diverse standards
  such as SSTL, LVSTL etc., enabling designers to mix and match signaling p
 rotocols across the same device while covering a wide frequency range. I/O
  banks support voltages from 0.5V to 3.3 V, including high-speed DDR PHY i
 nterfaces for LPDDR4/5 up to 3.2Gbps. Robust signal integrity across wide 
 frequency-voltage spectrum is achieved through on die IO PVT calibration w
 hich dynamically compensates for variations in silicon process, supply vol
 tage, temperature ensuring consistent electrical characteristics like outp
 ut drive strength and termination impedance. A SAR-based digital block and
  analog block collaboratively manage reference currents and voltages resul
 ting in complex mixed-signal system.\n\nVerification of this subsystem is 
 paramount to prevent chip-level failures. Full-chip verification challenge
 s include multiple IO banks distributed across chip periphery and CPU-indi
 vidual bank connections. Validating signal paths from CPU to farthest IO b
 ank necessitates analyzing significant portion of the chip, leading to inc
 reased simulation runtime and memory usage. \n\nThis presentation covers P
 VT calibration architecture and verification strategies. It highlights how
  Siemens Symphony Pro optimizes debugging, reduces simulation time by ~3x,
  improves memory usage by ~2-3x, and streamlines regressions ensuring reli
 able calibration verification across diverse I/O standards and extreme PVT
  conditions.\n\nTopics: AI, Chiplet, Design, EDA, Quantum, Security, Syste
 ms\n\n
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