BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
X-LIC-LOCATION:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20260730T152729Z
LOCATION:DAC Pavilion\, Exhibit Floor
DTSTART;TZID=America/Los_Angeles:20260728T170000
DTEND;TZID=America/Los_Angeles:20260728T180000
UID:dac_DAC 2026_sess295_ENGPOST242@linklings.com
SUMMARY:A Hybrid Simulation and Formal Verification Approach for Exhaustiv
 e Interrupt and Status Flag Verification
DESCRIPTION:Giovanni Auditore, Jagriti Khurana, Shaifali Bansal, and Vikas
  Saurav (STMicroelectronics) and Archana Arya (ST Microelectronics)\n\nVer
 ification of status flags and interrupts is critical for correct interacti
 on between IP components, yet exhaustive validation of interrupt behavior 
 remains challenging when relying solely on simulation-based approaches. Th
 is approach presents a hybrid simulation and formal verification methodolo
 gy for interrupt and status flag verification using an interrupt Verificat
 ion IP (VIP) and demonstrates its application on a Real-Time Clock (RTC) I
 P. Simulation-based verification is used to validate interrupt behavior un
 der realistic programming scenarios, while formal verification is leverage
 d to exhaustively prove interrupt properties and corner cases that are dif
 ficult to cover in simulation. The results highlight the effectiveness of 
 combining dynamic and formal verification through a reusable interrupt ver
 ification infrastructure to improve confidence in interrupt correctness at
  the IP level.\n\nTopics: AI, Chiplet, Design, EDA, Quantum, Security, Sys
 tems\n\n
END:VEVENT
END:VCALENDAR