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BEGIN:VEVENT
DTSTAMP:20260730T152730Z
LOCATION:DAC Pavilion\, Exhibit Floor
DTSTART;TZID=America/Los_Angeles:20260728T170000
DTEND;TZID=America/Los_Angeles:20260728T180000
UID:dac_DAC 2026_sess295_ENGPOST237@linklings.com
SUMMARY:Novel approach to signoff large MRAM memory IP using Hierarchical 
 flow
DESCRIPTION:Dinesh Chandra, Sushma Sambtur, Deepak Kumar Sahoo, and Kumari
  Saumya Diwedi (GlobalFoundries) and Naveen B and Shreya Sashi (Synopsys)\
 n\nAt SOC level, customer requires comprehensive electrical views, of the 
 memory IP we design, to support Power and Reliability sign-off. Generating
  APL models requires waveform database (FSDB) from the spice simulation of
  the IP.  As IP size is very huge, full extracted macro simulations are no
 t practical. So, we have used a hierarchical approach using block level si
 mulations, without losing accuracy. We are able to generate model in reaso
 nable runtime. we compared the results from Hierarchical approach against 
 results from a flat run for the smallest IP, and the results are comparabl
 e.\n\nTopics: AI, Chiplet, Design, EDA, Quantum, Security, Systems\n\n
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