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BEGIN:VEVENT
DTSTAMP:20260730T152728Z
LOCATION:DAC Pavilion\, Exhibit Floor
DTSTART;TZID=America/Los_Angeles:20260728T170000
DTEND;TZID=America/Los_Angeles:20260728T180000
UID:dac_DAC 2026_sess295_ENGPOST216@linklings.com
SUMMARY:An Adaptive Dynamic Power Reduction Technique for Digital Filters
DESCRIPTION:Ankur Bal and Prince Bansal (STMicroelectronics) and Harvinder
  Singh (Synopsys)\n\nDigital FIR filters are typically designed for worst-
 case full-scale input precision, resulting in unnecessary dynamic power di
 ssipation when processing low-amplitude signals. This paper introduces an 
 adaptive technique that tracks real-time signal dynamic range and selectiv
 ely disables toggling of sign-extended bits in datapath registers. By gati
 ng both data and clock for these redundant bits, the approach significantl
 y reduces switching activity without impacting filter functionality or per
 formance. Demonstrated on a 20-tap FIR filter in 28nm FDSOI technology, th
 e proposed architecture achieved over 7% total power savings for a wideban
 d OFDM signal with -24 dB input amplitude. The solution is fully digital, 
 incurs minimal hardware overhead, and is easily deployable across existing
  filter architectures and technologies. Furthermore, it is scalable to oth
 er shift-register-based structures such as delay chains and FIFOs, making 
 it a practical and efficient method for dynamic power reduction in contemp
 orary signal processing systems.\n\nTopics: AI, Chiplet, Design, EDA, Quan
 tum, Security, Systems\n\n
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