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DTSTAMP:20260730T152728Z
LOCATION:DAC Pavilion\, Exhibit Floor
DTSTART;TZID=America/Los_Angeles:20260728T170000
DTEND;TZID=America/Los_Angeles:20260728T180000
UID:dac_DAC 2026_sess295_ENGPOST215@linklings.com
SUMMARY:A Compact Digital IP for FMCW Chirp Linearity Monitoring in Automo
 tive Radar Systems
DESCRIPTION:Ankur Bal, Prince Bansal, and Jeet Tiwari (STMicroelectronics)
  and Harvinder Singh (Synopsys)\n\nAutomotive radar systems rely on highly
  linear FMCW chirp signals to ensure accurate distance and velocity measur
 ements for ADAS applications. Deviations in chirp linearity can compromise
  radar performance and violate functional safety standards. This paper pre
 sents a compact, all-digital IP for real-time chirp linearity monitoring i
 ntegrated within the radar transmitter subsystem. The proposed solution le
 verages zero-crossing alignment between the chirp signal and an on-chip re
 ference clock to compute instantaneous frequency slope deviations without 
 requiring dedicated high-frequency clocks. The architecture includes count
 ers, edge overlap detection, and an error computation engine, demonstrates
  detection of minor deviations as low as 0.001% across a 10 μs chirp durat
 ion. Implemented entirely in digital logic, the IP is technology-independe
 nt, incurs less than 5% area overhead, and operates with any available on-
 chip clock source. This scalable, low-cost solution enhances radar transmi
 tter reliability and supports compliance with automotive safety standards,
  making it ideal for integration into next-generation radar SoCs.\n\nTopic
 s: AI, Chiplet, Design, EDA, Quantum, Security, Systems\n\n
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