BEGIN:VCALENDAR VERSION:2.0 PRODID:Linklings LLC BEGIN:VTIMEZONE TZID:America/Los_Angeles X-LIC-LOCATION:America/Los_Angeles BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:19700308T020000 RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:19701101T020000 RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20260730T152729Z LOCATION:DAC Pavilion\, Exhibit Floor DTSTART;TZID=America/Los_Angeles:20260728T170000 DTEND;TZID=America/Los_Angeles:20260728T180000 UID:dac_DAC 2026_sess295_ENGPOST212@linklings.com SUMMARY:RDC Methodology: Noise Reduction and Improving Accuracy DESCRIPTION:Sushovan Kunti and Megha Hansaliya (Google)\n\nBackground:\nRD C analysis is crucial for ensuring the robustness and reliability of compl ex digital designs. Reset Domain Crossing analysis is a part of Sign-Off c hecks in today's design. Due to complexity of the design, a huge number of reset domains and asynchronous resets require a proper reset domain cros sing sign-off methodology to avoid metastability, glitches and other funct ional problems. However, traditional RDC verification methodologies often generate excessive noise and violations, hindering accurate identification of genuine issues. This paper presents a novel approach to significantly reduce noise and enhance result accuracy in RDC analysis by leveraging two key features, Skip Resetless Flow and 3PIP Soft Reset Handling.\n\nMethod ology:\nIn the RDC flow, designers are expected to enable these features. Let's understand the functionality of both of these features to start with ,\n\n1. Skip Resetless Flow:\nIn today's modern design we use restless flo ps to reduce the power consumption, silicon area and improve the timing pe rformance. Most of the cases these flops are placed so to keep in mind tha t reset path will not contribute to the metastability of the design.\nUsin g the skip_resetless flow, we address the challenge of false violations ar ising from the propagation of data corruption through resetless flops in c urrent flow. In conventional RDC analysis the tools are primarily configur ed to propagate corruption and report violations on the first sequential e lement after the source, even if these elements are resetless flop. Most o f the time restless flops are not contributing any metastability. This lea ds to an inflated number of violations, obscuring critical RDC issues and prolonging verification cycles.\nOur proposed solution utilizes the skip_r esetless_flops argument within the RDC flow. By setting this argument to t rue, we enable the "Skip Resetless Flow" effectively bypassing the propaga tion of corruption through resetless flops. This targeted approach signifi cantly reduces the number of reported violations and focuses attention on genuine RDC hazards.\nIn the below design, if the skip_resetless_flops arg ument is set to true, RDC tool skips the dest1, skip1, and the skip2 reset less flops and reports a violation between the src1 [rst1] and obs_seq [rs t2]. \n\nNote: Sequential elements with asynchronous set/reset pins tied t o an inactive constant values are also treated as resetless flops, such as , dest1 and skip2, in the above case.\n\n2. 3rd-Party IPs Soft Reset Handl ing:\nHandling 3rd-Party IPs is the most crucial problem statement we have in our current design as lots of 3PIPs are used today. Most of the time t hese IPs are not run flat at block level to reduce the runtime and unneces sary debugging within the IPs. In current methodology, when we blackbox th ese IPs, all reset interfaces are treated as asynchronous and create lots of violations between 3PIP and block level logic.\nWith this new custom co nfiguration, users will have the liberty to perform soft-reset analysis fo r RDC paths that are interacting between internal to the 3PIP and the exte rnal paths effectively without considering all reset paths as asynchronous . In this approach it will still consider these 3rd-Party IPs as blackbox and will analyse without affecting runtime of the tool. \n\nConfig Setting : configure_setup_check -enable_ip_block_check_for_soft_reset true\nUsage: configure_ip_block -names { <3PIP list with space separated>}\n\nListed b elow are some example scenarios which will give more clarity on the scenar ios that would be covered or not covered as part of this methodology.\n\n1 . Scenarios where soft-resets generated internally to the 3PIP and also co nsumed internally, won't be considered for the analysis. \n2. Scenarios where resets or soft-resets generated internally to the 3PIP but getting c onsumed externally, will be considered for the analysis.\n3. Scenarios whe re resets or soft-resets generated externally to the 3PIP but getting cons umed internally in the 3PIP, will be considered for the analysis.\n\nResul ts and Conclusions:\nDesign Soft-Resets Reported\n With config uration Without configuration\nSubSystem_1 403 707\nSubSystem_2 5 13\ nSubSystem_3 67 567\n\nIn conclusion, this methodology demonstrates the usage of the "Skip Resetless Flow" and "3rd Party IPs Soft Reset Handling" in refi ning RDC analysis by minimizing noise and pinpointing genuine violations. By strategically bypassing resetless flops, this method offers a more prec ise and efficient approach to identifying and mitigating RDC hazards, ulti mately leading to more reliable designs. Furthermore, we extend this enhan cement by introducing custom configuration for "3rd Party IPs soft-reset h andling." This feature allows users to selectively analyze RDC paths inter acting between internal and external domains of a 3PIP, enabling focused v erification of critical reset behaviors and also reducing the noise. The c ombined application of "Skip Resetless Flow" and tailored "3PIP Soft-reset handling" provides a comprehensive and efficient solution for robust RDC verification in complex digital designs.\n\nApplicability:\nHighly applica ble to a broad range of users dealing with complex SoCs, especially those utilizing numerous reset domains, asynchronous resets, and 3rd-Party IPs.\ nThe techniques are readily implementable within standard RDC tool flows.\ n\nChallenge/Idea:\nThe fundamental issue of false violations due to reset less flops and blackboxed 3rd-Party IPs reset handling is a common industr y problem. However, the specific combination and implementation of "Skip R esetless Flow" and "3rd-Party IPs Soft Reset Handling" provides a novel an d effective solution.\n\nNovelty:\nTraditional RDC analysis often treats a ll reset crossings as potential hazards, leading to a high volume of false positives. This submission introduces targeted filtering. The "Skip Reset less Flow" provides a precise mechanism to bypass known non-contributing r esetless flops, significantly reducing noise.\nThe "3rd-Party IP Soft Rese t Handling" provides a custom configuration that allows the user to perfor m soft-reset analysis for RDC paths that are interacting between internal to the 3PIP and the external paths. Standard industry practices often stru ggle to efficiently handle reset interactions with blackboxed 3rd-Party IP s, leading to either excessive violations or incomplete analysis. This com bination provides a very detailed and customizable approach to RDC analysi s that is not commonly seen.\n\nTopics: AI, Chiplet, Design, EDA, Quantum, Security, Systems\n\n END:VEVENT END:VCALENDAR