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DTSTAMP:20260730T152729Z
LOCATION:DAC Pavilion\, Exhibit Floor
DTSTART;TZID=America/Los_Angeles:20260728T170000
DTEND;TZID=America/Los_Angeles:20260728T180000
UID:dac_DAC 2026_sess295_ENGPOST188@linklings.com
SUMMARY:A Novel Methodology for Automated LVS Rule Deck Verification: Trut
 h Table and Device Extraction Qualification
DESCRIPTION:Ahmed Saleh (Siemens); Jaeyoung So, Minho Jung, Heejae Lim, Ji
 min Yeo, Yunseong Lee, and Jiyoung Shin (Samsung Electronics); and Mohamed
  Alimam (Siemens)\n\nModern semiconductor fabrication faces an escalating 
 verification challenge as technology nodes shrink to 3nm and beyond, where
  Layout Versus Schematic (LVS) verification complexity has grown exponenti
 ally. Today's LVS must go beyond comparing Schematic and Layout designs; i
 t must extract R/C values for hundreds of devices, perform parasitic extra
 ction (PEX), and analyze complex CAD layer interactions. At 3nm nodes, dev
 ice extraction requires 30 to 50 CAD layers per device due to Mask Data Pr
 eparation (MDP) demands, making manual verification infeasible. This paper
  presents a novel automated Device Extraction Quality Assurance (QA) frame
 work integrating three verification engines: Truth Table Checker, Compare 
 Checker, and Device Extraction QA. The workflow ensures device extraction 
 is properly performed as described by process development, extracting layo
 uts from seed layers and supplying devices to SPICE netlists for simulatio
 n-based verification. Validated across technologies from 8-12 inch legacy 
 processes to 3nm nodes, the framework enables early detection of truth tab
 le errors and parasitic device extraction issues through automated paramet
 er qualification. The truth table checker flow has dramatically reduced tu
 rn-around time to rule deck release while significantly improving quality.
  With average runtimes under 30 minutes, qualification engineers receive c
 omprehensive reports clearly indicating where attention is needed, enablin
 g rapid issue resolution and high-confidence PDK releases.\n\nTopics: AI, 
 Chiplet, Design, EDA, Quantum, Security, Systems\n\n
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