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DTSTAMP:20260730T152727Z
LOCATION:DAC Pavilion\, Exhibit Floor
DTSTART;TZID=America/Los_Angeles:20260728T170000
DTEND;TZID=America/Los_Angeles:20260728T180000
UID:dac_DAC 2026_sess295_ENGPOST161@linklings.com
SUMMARY:Library PPA DTCO with Library Profiler
DESCRIPTION:Jaehwan Jeon, Inguk Min, Ilsu Son, and Byungsu Kim (Samsung El
 ectronics) and Ahyoung Kwak and Connor Schentag (Siemens)\n\nStandard cell
  technology is advancing rapidly, with each new generation introducing gre
 ater complexity and heightened design challenges. As designs evolve, meeti
 ng critical design goals across new processes becomes increasingly demandi
 ng, making Design-Technology Co-Optimization (DTCO) more important than ev
 er. To support these goals and address rising expectations for performance
 , efficiency, and scale, designers rely on quantifying and comparing IPs u
 sing Power, Performance, and Area (PPA) metrics. These PPA values, extract
 ed from Liberty (.lib) data, play a crucial role in enabling early IP sele
 ction during the design flow.\n\nA key to measuring the progress of each t
 echnology node is the ability to compare it against past designs and proce
 sses. Historically, specialized tools for precise cell-to-cell PPA analysi
 s across different technologies did not exist, making trend verification a
 nd anomaly detection challenging. Effective cross-technology comparisons w
 ould help designers confirm expected improvements or identify outlier resu
 lts.\n\nThis paper presents a novel approach utilizing Siemens' Solido Lib
 rary Profiler solution to perform robust PPA analysis across multiple tech
 nologies. By efficiently extracting, loading, and storing PPA data, this t
 ool enables quick, visual comparison of new and legacy technologies, suppo
 rting comprehensive DTCO activities and confident development direction.\n
 \nTopics: AI, Chiplet, Design, EDA, Quantum, Security, Systems\n\n
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