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DTSTAMP:20260730T152727Z
LOCATION:DAC Pavilion\, Exhibit Floor
DTSTART;TZID=America/Los_Angeles:20260728T170000
DTEND;TZID=America/Los_Angeles:20260728T180000
UID:dac_DAC 2026_sess295_ENGPOST152@linklings.com
SUMMARY:VeriScore: Measuring LLM Verification Quality with Mutation- and S
 oundness-Based Metrics
DESCRIPTION:Rohil Khare and Tamzid Razzaque (SigmanticAI)\n\nLarge languag
 e models are increasingly used to generate hardware verification artifacts
  from natural language prompts, yet evaluation is often limited to syntact
 ic or build success. We present VeriScore, an open evaluation framework th
 at measures end to end verification quality by executing generated verific
 ation artifacts on correct and systematically mutated RTL designs. VeriSco
 re provides standardized prompts with explicit assumptions, golden RTL imp
 lementations, and controlled bug injected mutants representing common hard
 ware error patterns. Generated artifacts such as assertions, checkers, tes
 tbenches, and harness code are built and executed under fixed resource bud
 gets and scored based on their ability to detect injected bugs without pro
 ducing false failures. In addition, VeriScore can optionally benchmark mod
 els against a curated suite of known correct verification artifacts derive
 d from design specifications, enabling direct comparison to reference asse
 rtions and checkers. The resulting report decomposes performance into buil
 dability, soundness, sensitivity, and non triviality and aggregates these 
 into a transparent prompt to verification accuracy score. VeriScore enable
 s reproducible tool agnostic comparison of verification pipelines and esta
 blishes a benchmark for evaluating verification effectiveness beyond compi
 lation.\n\nTopics: AI, Chiplet, Design, EDA, Quantum, Security, Systems\n\
 n
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