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DTSTAMP:20260730T152727Z
LOCATION:DAC Pavilion\, Exhibit Floor
DTSTART;TZID=America/Los_Angeles:20260728T170000
DTEND;TZID=America/Los_Angeles:20260728T180000
UID:dac_DAC 2026_sess295_ENGPOST145@linklings.com
SUMMARY:Early, efficient and scalable parasitic-aware layout design method
 ology for high-precision ICs
DESCRIPTION:Kopal Kulshreshtha (Synopsys) and Emmanuele Mazzará (NXP)\n\nD
 ue to the increasing size and complexity of high-performance integrated ci
 rcuits (ICs), especially in advanced technology nodes, the influence of pa
 rasitics on the layout has become dominant.  Traditional signoff tools and
  internal scripts often suffer from slow execution, challenging maintenanc
 e, and insufficient precision, which limits their effectiveness in address
 ing the stringent requirements of precision ICs. \n\nTo overcome these lim
 itations, a systematic flow for early IC layout parasitic analysis has bee
 n developed for quick and efficient detection and debug of parasitic viola
 tions. Our shift-left methodology establishes a framework for defining con
 straints upfront on all critical design nets, enables comparison of multip
 le layout revisions and provides unique capabilities for verifying large t
 op-level design hierarchies - ensuring robust coverage across diverse desi
 gn teams and technology nodes. \n\nThe flow's scalability allows its adopt
 ion for various design styles, facilitating early detection, debugging, an
 d resolution of even minute parasitic violations that would otherwise requ
 ire lengthy simulation cycles. As a result, design time is significantly r
 educed by minimizing iterative simulation runs, leading to substantial sav
 ings in hardware resources and software license requirements for simulatio
 n tools. This systematic early parasitic analysis flow represents a transf
 ormative advancement for precision IC development, delivering enhanced des
 ign quality, reliability, and productivity.\n\nTopics: AI, Chiplet, Design
 , EDA, Quantum, Security, Systems\n\n
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