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DTSTAMP:20260730T152727Z
LOCATION:DAC Pavilion\, Exhibit Floor
DTSTART;TZID=America/Los_Angeles:20260728T170000
DTEND;TZID=America/Los_Angeles:20260728T180000
UID:dac_DAC 2026_sess295_ENGPOST136@linklings.com
SUMMARY:Accelerating IR and Timing Convergence with Revolutionary IR-ECO
DESCRIPTION:Ping Ding, Tuo Wang, and Guohua Zhou (Sanechips) and Li Zou an
 d Chang Zhao (Synopsys)\n\nComplex applications (such as AI & HPC) and adv
 anced tech nodes are driving a dramatic increase in design scale and compl
 exity. It's currently impractical to construct a robust power delivery net
 work (PDN) by consuming a large amount of design resources and the higher 
 local cell density causes worse voltage drop(IR) violations than ever befo
 re. At the same time, the margin of the process is decreasing continuously
 , the influence of voltage drop on timing is becoming increasing prominent
 . Therefore, it becomes crucial to establish the correlation between IR an
 d timing to avoid over-fixing.\nIn traditional flow,\n§        We fix IR v
 iolations by fixing thousands of violation instances(victims). However, th
 is approach has a low profit. It takes multiple manual iterations to resol
 ve the violations, because the root cause of the violations(aggressors) is
  not identified.\n§        The impact on timing cannot be considered durin
 g the manual IR violation fix cycles. Meanwhile, an instance with IR issue
  is usually also an instance that is sensitive to the timing. In this case
 , we finally need to perform a hard tradeoff between IR and timing.\n§    
     Separated IR and Timing ECOs are very time consuming, costly and alway
 s posed significant challenges for design closure within tape-out timeline
 s. \n   To minimize iteration counts and design changes, avoid timing degr
 adation or chip failure, an automated late-stage timing-aware IR fix metho
 dology is proposed here. The joint IR-ECO flow ensures seamless communicat
 ion between the golden ECO tool PrimeClosure and golden IR/EM analysis too
 l RedHawk-SC, enables accurate identification of root cause aggressors, pr
 ovides immediate feedback on the voltage impact of ECO operations proposed
  by PrimeClosure, and automatically fixes IR violations without timing hur
 t.\n   In our design, IR-ECO can fix over 60% of signoff-stage IR violatio
 ns within a few hours, and introducing few/no negative impact on timing, w
 hich is very important for timing- critical blocks. Minimum number of inst
 ances changed by addressing aggressors. Fewer design change operations and
  minimum iterations can save several weeks of iteration period than tradit
 ional flow. This offering better PPA and significantly boosts the time to 
 tape out. \nkeywords : IR-ECO, IR-timing closure, aggressor analytics, tim
 ing-aware IR fix\n\nTopics: AI, Chiplet, Design, EDA, Quantum, Security, S
 ystems\n\n
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