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DTSTAMP:20260730T152728Z
LOCATION:DAC Pavilion\, Exhibit Floor
DTSTART;TZID=America/Los_Angeles:20260728T170000
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UID:dac_DAC 2026_sess295_ENGPOST134@linklings.com
SUMMARY:Accelerating CPU Design in Advanced Nodes with  AI-Powered Floor p
 lanning and VT Optimization
DESCRIPTION:Lakshmidas K and Gowry Shanmugam (Cadence Design Systems, Inc.
 )\n\nAs technology nodes scale into the angstrom regime, design complexity
  has surged due to stringent performance, power, and area (PPA) targets an
 d the need to manage diverse cell libraries across multiple PVT corners. A
 chieving optimal cell selection, macro placement, and layer distribution u
 nder these conditions is highly challenging, making manual tuning impracti
 cal given tight timing closure, power budgets, VT proliferation, and floor
 plan sensitivity. Automation is now essential to enable systematic design 
 space exploration and maintain competitiveness.\nThis paper presents an AI
 -driven approach to automate floorplanning and VT optimization for macro-d
 ominated, high-frequency CPU designs in sub-nanometer nodes. The proposed 
 solution integrates VT-Optimizer (VT-Opt), which tunes multi-VT flows by g
 enerating adaptive VT recipes and validating them through full-flow runs, 
 and FP-Opt, which explores alternative floorplans by adjusting bounding bo
 xes, aspect ratios, and macro placements while targeting utilization, cong
 estion, timing, and power. Optimal configurations are selected based on fu
 ll-flow evaluations, followed by PPA optimization to achieve best-in-class
  results.\nThe methodology significantly reduces design turnaround time, m
 itigates risk, and improves PPA, demonstrating its effectiveness for next-
 generation CPU designs.\n\nTopics: AI, Chiplet, Design, EDA, Quantum, Secu
 rity, Systems\n\n
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