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BEGIN:VEVENT
DTSTAMP:20260730T152728Z
LOCATION:DAC Pavilion\, Exhibit Floor
DTSTART;TZID=America/Los_Angeles:20260728T170000
DTEND;TZID=America/Los_Angeles:20260728T180000
UID:dac_DAC 2026_sess295_ENGPOST113@linklings.com
SUMMARY:AI&Cell based Analog Circuit Topology Generator(CTGEN)
DESCRIPTION:Akira KURUSU, Kouji HIRAI, Shigeya YAMAGUCHI, Jin WATANABE, Ta
 kuto OGURA, Chao GENG, Masanori KUSANO, Ryou HAMADA, Kazuhiro KUDO, and No
 buto ono (Jedat Inc.); Tsuyoshi MASUBUCHI and Nobukazu TAKAI (Kyoto Instit
 ute of Technology); Shigetoshi NAKATAKE (University of Kitakyushu); and Te
 tsuya IIZUKA (The University of Tokyo)\n\nThis provides the new analog des
 ign methodology which will generates schematic topology for practical usag
 e.\nThe abstract concept of topology generation is following.\nDecompose t
 he many circuits schematic resources to small cells or blocks.\nThen const
 ruct for the best combination topology to meet the each specific target un
 der spice simulation base optimization for block level architecture schema
 tic.  This design could be existing schematic but partially structured as 
 blocks which internally build by connected between selectable libraries' c
 ells or blocks.\nEach cell and block are already validated and parametric 
 , the final schematic is acceptable by designers.\nThis tool is independen
 t from circuit categories and any process. The evaluations are from spice 
 simulation under PDK from testbenches.\nThis may produce better combined c
 ircuit topology than depending on designers experiences or skill. \nThe ke
 y technologies of this tool are\n1. AI searching method in huge combinator
 ial space which is used like Alpha-GO\n2. Recent Machine learning algorith
 m for circuit parameter optimization\n3. Dived the stage as learning and i
 nference which scalable by machine resources\nThis will improve the reusab
 ility and improve migration efficiency equipped with topology changing.\nT
 he final design sign off could be done in current customers design environ
 ments.\n\nTopics: AI, Chiplet, Design, EDA, Quantum, Security, Systems\n\n
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