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BEGIN:VEVENT
DTSTAMP:20260730T152729Z
LOCATION:DAC Pavilion\, Exhibit Floor
DTSTART;TZID=America/Los_Angeles:20260728T170000
DTEND;TZID=America/Los_Angeles:20260728T180000
UID:dac_DAC 2026_sess295_ENGPOST110@linklings.com
SUMMARY:A Simple and Predictable Solution for Early Full-Chip LVS converge
 nce
DESCRIPTION:Ravidas Damodaran, Tayib Samu, Kumaresan Vallinayagam, and Vis
 hnu Chandrakar (Intel)\n\nFor Large designs with multiple levels of hierar
 chies, predicting LVS convergence is very challenging if there are power a
 nd ground shorts and opens especially across hierarchies, as its debug cou
 ld be time consuming and iterative. Also, it is difficult to identify all 
 integration issues at next hierarchy level if any partition is LVS dirty. 
 There are inherent disadvantages in traditional techniques such as black b
 ox LVS and destructive cleanup approach that can enable hierarchical level
  LVS run. To overcome these shortcomings, a simple and efficient solution 
 which can be implemented at any stage of the partition's APR flow from flo
 orplan to route, is described. In this solution critical interface details
  like Power-Ground network, global clock and signal routes which are pushe
 d down to partitions, hard macros and partition ports are retained and are
  made LVS clean using this automated flow. This solution was wildly used f
 or many partitions to identify and fix LVS issues accurately early on in m
 ultiple projects and enabled timely SoC tape-outs. This solution enabled s
 eamless integration of late-coming partitions, as all the risks with integ
 ration were identified and fixed upfront.\n\nTopics: AI, Chiplet, Design, 
 EDA, Quantum, Security, Systems\n\n
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