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BEGIN:VEVENT
DTSTAMP:20260715T200609Z
LOCATION:DAC Pavilion\, Exhibit Floor
DTSTART;TZID=America/Los_Angeles:20260728T170000
DTEND;TZID=America/Los_Angeles:20260728T180000
UID:dac_DAC 2026_sess295_ENGPOST104@linklings.com
SUMMARY:Breaking the simulation wall – practical acceleration for pre-sili
 con validation
DESCRIPTION:Sundarraj Durairaj, Vaibhav Kumar, Tauqueer Alam, and Ragavend
 ar Swamisai (NXP) and David Chao and Manik Chugh (Siemens)\n\nNext-generat
 ion SoCs demand robust and high-confidence DDR subsystem verification, yet
  traditional simulation struggles to keep pace. Long-duration DDR behavior
 s—such as training loops, refresh cycles, retention checks, and hours of s
 ustained traffic—consume excessive simulation time and slow down project v
 elocity. These time-intensive patterns often stall coverage closure, push 
 out debug windows, and delay subsystem readiness.\n\nThis work showcases a
  high-performance verification acceleration strategy using the Siemens Vel
 oce Strato CS hardware emulation platform to remove these bottlenecks. By 
 transitioning existing UVM stimulus into an emulation-optimized transactor
  environment, the flow executes long-running DDR workloads at speed order 
 of magnitude faster while maintaining cycle-accurate behavior and full deb
 ug correlation. The result is faster iteration, increased test throughput,
  and earlier discovery of timing-sensitive issues that rarely surface in c
 onventional simulation schedules.\n\nKey highlights include an optimized D
 DR command/data transactor architecture for emulation, transparent reuse o
 f simulation sequences, and targeted debug techniques purpose-built for ha
 rdware-assisted verification. This accelerated DDR flow enables teams to r
 un extensive, hours-to-days traffic profiles within practical timelines—tr
 ansforming verification productivity and delivering higher confidence in s
 ubsystem quality ahead of tape-out.\n\nTopics: AI, Chiplet, Design, EDA, Q
 uantum, Security, Systems\n\n
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