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DTSTAMP:20260730T152728Z
LOCATION:DAC Pavilion\, Exhibit Floor
DTSTART;TZID=America/Los_Angeles:20260728T170000
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UID:dac_DAC 2026_sess295_ENGPOST087@linklings.com
SUMMARY:Cognitively Guided EM-Aware Routing Approach for Efficient Layout 
 Implementation
DESCRIPTION:Akshita Bansal and Sachin Bhasin (Cadence Design Systems, Inc.
 ) and Rajeev Singh and Nisha Rana (STMicroelectronics)\n\nElectromigration
  (EM) and resistance constraints are traditionally verified at sign-off, m
 aking routing electrically blind and leading to costly post-layout iterati
 ons. This paper introduces a simulation-driven routing (SDR) methodology t
 hat integrates electrical intent into the layout process, enabling EM-corr
 ect-by-construction routing. The proposed approach leverages average curre
 nt datasets from circuit simulation or design intent (DI) set in schematic
  database to dynamically guide routing decisions. For optimal routing the 
 automation implements customizable trunk stacking across multiple metal la
 yers, optimized trunk widths for area efficiency, and uniform via distribu
 tion to minimize resistance. SDR supports configurable stacking strategies
 —Auto, Trunk, and Custom—allowing full user control through SKILL-based mo
 difications for scalability across nodes. Visualization of current distrib
 ution further enhance topology optimization. Implemented on a 28nm analog 
 design, the methodology achieves routing quality equivalent to golden refe
 rence while reducing EM sign-off iterations and manual effort. Results dem
 onstrate 30% faster turnaround, zero area wastage, and improved reliabilit
 y without compromising design integrity. This framework addresses critical
  pain points in conventional flows and provides a scalable solution for hi
 gh-current nets in both mature and advanced technologies.\n\nTopics: AI, C
 hiplet, Design, EDA, Quantum, Security, Systems\n\n
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