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DTSTAMP:20260730T152729Z
LOCATION:DAC Pavilion\, Exhibit Floor
DTSTART;TZID=America/Los_Angeles:20260728T170000
DTEND;TZID=America/Los_Angeles:20260728T180000
UID:dac_DAC 2026_sess295_ENGPOST085@linklings.com
SUMMARY:AI-Enabled Flow for Silicon Area Reduction and Design Closure
DESCRIPTION:saurabh gautam and anil yadav (STMicroelectronics)\n\nAbstract
 —Artificial Intelligence (AI) has emerged as a transfor-\nmative technolog
 y in electronic design automation (EDA) flows,\nenabling significant impro
 vements in power, performance, and\narea (PPA) metrics. This paper explore
 s the critical role of AI-\ndriven techniques in optimizing semiconductor 
 design processes,\nhighlighting how intelligent algorithms can automate de
 cision-\nmaking, predict optimal design parameters, and effectively re-\nd
 uce silicon area. By integrating AI into the design flow, users can\nachie
 ve enhanced PPA trade-offs, minimize manual intervention,\nand accelerate 
 time-to-market. The study demonstrates practical\nmethodologies and case s
 tudies illustrating how AI empowers\ndesigners to optimize chip layouts, i
 mprove resource utilization,\nand achieve superior silicon efficiency.\n\n
 Index Terms—EDA, PPA, Artificial Intelligence, Floorplanning,\nSilicon Are
 a Reduction\n\nTopics: AI, Chiplet, Design, EDA, Quantum, Security, System
 s\n\n
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