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BEGIN:VEVENT
DTSTAMP:20260730T152728Z
LOCATION:DAC Pavilion\, Exhibit Floor
DTSTART;TZID=America/Los_Angeles:20260728T170000
DTEND;TZID=America/Los_Angeles:20260728T180000
UID:dac_DAC 2026_sess295_ENGPOST080@linklings.com
SUMMARY:Routability Optimizing Methodology Using Flexible Pin
DESCRIPTION:Jinman Kang, Chaewon Song, Heeyoung Moon, Sangdo Park, Jun Seo
 mun, and Hyung-Ock Kim (Samsung Electronics)\n\nWe introduce a new design 
 method to optimize routability through flexible pin.\nIt contributes to se
 curing routing resources for the entire block by using flexible pins, whic
 h provide multiple pin‑access points on the highly congested lower metal l
 ayers of advanced node technologies, together with a new integrated DRC an
 d LVS checking flow.\nWe propose two methods: ① Flexible Pin Location and 
 ② Flexible Pin Shape. Each method expands the set of pin‑connection candid
 ates according to the surrounding routing congestion, thereby improving th
 e overall routing resources of the block.\nIn this work, we observed a not
 iceable decrease in the detour ratio on critical paths 16.05% for Flexible
  Pin Location and 63.60% for Flexible Pin Shape, compared with the fixed‑p
 in case, achieved by increasing the number of connection candidates or by 
 reducing displacement during cell moves.\nIn addition, the proposed method
 s show a reduction in net delay on critical paths 1.77% for Flexible Pin L
 ocation and 8.84% for Flexible Pin Shape, resulting in Fmax improvements f
 or the respective cases, as demonstrated on an industrial test case with a
  seamless flow.\n\nTopics: AI, Chiplet, Design, EDA, Quantum, Security, Sy
 stems\n\n
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