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DTSTAMP:20260730T152726Z
LOCATION:DAC Pavilion\, Exhibit Floor
DTSTART;TZID=America/Los_Angeles:20260728T170000
DTEND;TZID=America/Los_Angeles:20260728T180000
UID:dac_DAC 2026_sess295_ENGPOST046@linklings.com
SUMMARY:Resistive model-based via optimizatiion
DESCRIPTION:Heng Lan Lau (Siemens)\n\nEMIR is a factor in chip performance
  and long-term reliability. Steps to address different causes of EMIR issu
 es are taken across a number of tools in any design flow methodology. At t
 he very last stage of the design cycle, via insertion by a EDA tool, such 
 as Calibre DesignEnhancer is the last attempt to further optimize via arra
 ngements in the physical chip design. The approach of via insertion by mos
 t software is an area-based computation. This paper discusses the benefits
  of a resistive model-based computation and suggests an implementation met
 hodology. For proof-of-concept, the model used in this paper is fictional,
  but it illustrates the impact of resistance-based via selection on the ul
 timate aim of reducing EMIR in the face of increasing via choices of futur
 e technology.\n\nTopics: AI, Chiplet, Design, EDA, Quantum, Security, Syst
 ems\n\n
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