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DTSTART:19700308T020000
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BEGIN:VEVENT
DTSTAMP:20260730T152729Z
LOCATION:DAC Pavilion\, Exhibit Floor
DTSTART;TZID=America/Los_Angeles:20260728T170000
DTEND;TZID=America/Los_Angeles:20260728T180000
UID:dac_DAC 2026_sess295_ENGPOST040@linklings.com
SUMMARY:A Chip-Level DTCO Framework for Yield-Aware Back-End Design: Layou
 t-Aware Misalignment Correction in DRAM
DESCRIPTION:HyeJin Kim (Samsung Electronics) and SoYoung Kim (Sungkyunkwan
  University)\n\nWe propose a chip-level, layout-aware DTCO framework to co
 rrect deterministic interlayer misalignment. Using layout-driven features 
 and machine learning, the proposed approach achieves ~70% variation reduct
 ion, enables fast inline prediction, and improves yield on silicon-proven 
 products.\n\nTopics: AI, Chiplet, Design, EDA, Quantum, Security, Systems\
 n\n
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