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DTSTAMP:20260730T152729Z
LOCATION:DAC Pavilion\, Exhibit Floor
DTSTART;TZID=America/Los_Angeles:20260728T170000
DTEND;TZID=America/Los_Angeles:20260728T180000
UID:dac_DAC 2026_sess295_ENGPOST021@linklings.com
SUMMARY:Novel methodology to replace OpenAccess inputs for hierarchical ch
 ip construction
DESCRIPTION:Eduard Herkel, Jesse Surprise, Joel Earl, and Gregory Schaeffe
 r (IBM Research)\n\nState-of-the-art microprocessors become more complex w
 ith every generation. Therefore, large microprocessor designs are implemen
 ted hierarchically. For Physical Design this means smaller building blocks
  are being processed from RTL to GDS first. Following, these pre-built blo
 cks can be integrated at higher levels with a final chip-wide place and ro
 ute as well as checking being done at the end. This process requires a pre
 cise handoff which for shapes is represented in form of a physical abstrac
 t. In the past, abstracts were created upfront on a higher level to includ
 e in-context information and were published as OpenAccess data to be used 
 as inputs for block construction. However, this process is very time consu
 ming, error prone and adds extra dependencies. The IBM z-Microprocessor te
 am has created a methodology where the OpenAccess views are being replaced
  by version-controlled text files. Generation of these text files is autom
 ated, depends on the latest RTL as well as the latest parent level state o
 f the design and runs independent of other processes. This simplifies the 
 hierarchical end-to-end pipeline from RTL to GDS because block specific OA
 -abstracts, required for construction, are generated on-the-fly. This not 
 only saves runtime but also increases the overall stability of the design.
 \n\nTopics: AI, Chiplet, Design, EDA, Quantum, Security, Systems\n\n
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