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LOCATION:DAC Pavilion\, Exhibit Floor
DTSTART;TZID=America/Los_Angeles:20260728T170000
DTEND;TZID=America/Los_Angeles:20260728T180000
UID:dac_DAC 2026_sess295@linklings.com
SUMMARY:Engineering Poster Session Two
DESCRIPTION:Design Verification Automation (DVA) for PCB Signal and Power 
 Integrity\n\nModern PCB designs contain thousands of signal nets operating
  up to multi-GHz frequencies, coupled with components requiring tight supp
 ly tolerances and increasing power demands through complex power distribut
 ion networks. These designs require comprehensive signal and power integri
 ty (SIPI) verific...\n\n\nSherif Amer, Adam El-Mansouri, Colton Love, Garr
 ett Stauffer, and Tracey Windley (Schweitzer Engineering Labs)\n----------
 -----------\nSlack-Exploiting Load Splitting for IR-Drop Mitigation\n\nMod
 ern ICs face severe IR-drop challenges, leading to timing violations and r
 eliability issues. Traditional mitigation methods like power grid reinforc
 ement or global buffer sizing incur significant area/power overheads, whil
 e IRECO often degrades performance due to tight timing budgets. This paper
  ...\n\n\nChou Hsiang (TSMC); Yu-Wen Lin, Wesley Hsieh, and Florin Dartu (
 Taiwan Semiconductor Manufacturing Company); and Charles Kuo and Nate Tai 
 (Synopsys)\n---------------------\nPhysics-Aware CNN-Based IR Drop Risk Pr
 ediction for Fast and Reliable SRAM Placement Optimization\n\nDynamic IR d
 rop in advanced nodes poses a critical challenge for SRAM memory placement
 , where dense instance packing and synchronized switching currents frequen
 tly cause localized power integrity violations. Conventional IR Drop analy
 sis relies on full-chip simulation after placement, making it impr...\n\n\
 nSeihyung Jang, HyoungRae Noh, yun ra, and sangkyoo jeong (SKhynix) and ka
 ram ahn and minjae chung (Synopsys)\n---------------------\nRDC Methodolog
 y: Noise Reduction and Improving Accuracy\n\nBackground:\nRDC analysis is 
 crucial for ensuring the robustness and reliability of complex digital des
 igns. Reset Domain Crossing analysis is a part of Sign-Off checks in today
 's design. Due to complexity of the design, a huge number of reset domains
  and asynchronous resets require a proper reset do...\n\n\nSushovan Kunti 
 and Megha Hansaliya (Google)\n---------------------\nUser Definable Custom
  Primitives in 3DIC AI-driven STCO: Case Study on Power Grid Optimization 
 for IR Enhancement\n\nIn AI-driven design optimization EDA flows, there is
  usually a pre-defined list of primitives, which are options or parameters
 , that the flow can experiment on. By fine-tuning primitive values using A
 I-driven algorithms and analysis, EDA flows aim to produce optimal PPA (pe
 rformance, power, and area...\n\n\nYi-Wei Chen, Chung-Ching Peng, and Vive
 k Rajan (Intel) and Xukang Wu, Xiaohu Xu, Sonia Beghum, Keshava Manimunda,
  Weifeng Gu, Hanqi Yang, and Pinhong Chen (Cadence Design Systems, Inc.)\n
 ---------------------\nEarly, efficient and scalable parasitic-aware layou
 t design methodology for high-precision ICs\n\nDue to the increasing size 
 and complexity of high-performance integrated circuits (ICs), especially i
 n advanced technology nodes, the influence of parasitics on the layout has
  become dominant.  Traditional signoff tools and internal scripts often su
 ffer from slow execution, challenging maintenance, ...\n\n\nKopal Kulshres
 htha (Synopsys) and Emmanuele Mazzará (NXP)\n---------------------\nResist
 ive model-based via optimizatiion\n\nEMIR is a factor in chip performance 
 and long-term reliability. Steps to address different causes of EMIR issue
 s are taken across a number of tools in any design flow methodology. At th
 e very last stage of the design cycle, via insertion by a EDA tool, such a
 s Calibre DesignEnhancer is the last atte...\n\n\nHeng Lan Lau (Siemens)\n
 ---------------------\nVeriScore: Measuring LLM Verification Quality with 
 Mutation- and Soundness-Based Metrics\n\nLarge language models are increas
 ingly used to generate hardware verification artifacts from natural langua
 ge prompts, yet evaluation is often limited to syntactic or build success.
  We present VeriScore, an open evaluation framework that measures end to e
 nd verification quality by executing generate...\n\n\nRohil Khare and Tamz
 id Razzaque (SigmanticAI)\n---------------------\nEarly Antenna Analysis f
 or IC Design: A Shift-Left Approach to Improve Productivity and Signoff Qu
 ality\n\nAntenna verification is a crucial step in physical design signoff
  to prevent transistor damage during IC fabrication. Traditional antenna D
 RC methods, however, are time-consuming and rely on short-free designs, ma
 king early analysis difficult when routing shorts or incomplete implementa
 tions exist. ...\n\n\nNagaMalleswari Metla, Praneeth Narsingoju, and Kalya
 naKumar Amruthuluri (Advanced Micro Devices (AMD)) and Basma Serry, Nermee
 n Hossam, and Mingyong Yu (Siemens)\n---------------------\nDifferential V
 alidator: Ensuring SoC ROM to Hierarchical Blocks Node Voltage Integrity\n
 \nSoC Flat IR/EM signoff is generally done for multiple cycles thus genera
 lly mandating 2+ days to cover a single scenario- not only is the coverage
  limited but also expensive since even small ECO fixes trigger full analys
 is repeat (of same resources).  Additionally, designs which have multiple 
 hierar...\n\n\nPRATEEK PENDYALA and Mathew Kaipanatu (Google) and Sai Atlu
 ri and Renjith R (Synopsys)\n---------------------\nA Compact Digital IP f
 or FMCW Chirp Linearity Monitoring in Automotive Radar Systems\n\nAutomoti
 ve radar systems rely on highly linear FMCW chirp signals to ensure accura
 te distance and velocity measurements for ADAS applications. Deviations in
  chirp linearity can compromise radar performance and violate functional s
 afety standards. This paper presents a compact, all-digital IP for rea...\
 n\n\nAnkur Bal, Prince Bansal, and Jeet Tiwari (STMicroelectronics) and Ha
 rvinder Singh (Synopsys)\n---------------------\nA Simple and Predictable 
 Solution for Early Full-Chip LVS convergence\n\nFor Large designs with mul
 tiple levels of hierarchies, predicting LVS convergence is very challengin
 g if there are power and ground shorts and opens especially across hierarc
 hies, as its debug could be time consuming and iterative. Also, it is diff
 icult to identify all integration issues at next hie...\n\n\nRavidas Damod
 aran, Tayib Samu, Kumaresan Vallinayagam, and Vishnu Chandrakar (Intel)\n-
 --------------------\nBreaking the simulation wall – practical acceleratio
 n for pre-silicon validation\n\nNext-generation SoCs demand robust and hig
 h-confidence DDR subsystem verification, yet traditional simulation strugg
 les to keep pace. Long-duration DDR behaviors—such as training loops, refr
 esh cycles, retention checks, and hours of sustained traffic—consume exces
 sive simulation time and slow down p...\n\n\nSundarraj Durairaj, Vaibhav K
 umar, Tauqueer Alam, and Ragavendar Swamisai (NXP) and David Chao and Mani
 k Chugh (Siemens)\n---------------------\nAccelerating CPU Design in Advan
 ced Nodes with  AI-Powered Floor planning and VT Optimization\n\nAs techno
 logy nodes scale into the angstrom regime, design complexity has surged du
 e to stringent performance, power, and area (PPA) targets and the need to 
 manage diverse cell libraries across multiple PVT corners. Achieving optim
 al cell selection, macro placement, and layer distribution under thes...\n
 \n\nLakshmidas K and Gowry Shanmugam (Cadence Design Systems, Inc.)\n-----
 ----------------\nMeeting EDA workload capacity needs with AWS for Siemens
 ' Solido Custom IC technologies\n\nThe collaboration between AWS and Sieme
 ns addresses the critical challenge of matching variable electronic design
  automation (EDA) computing demand with static on-premise resources, which
  is both difficult and capital intensive. Siemens' Solido Intelligent Cust
 om IC Verification, enabled by AWS clou...\n\n\nAzim Siddique (AWS) and Sa
 urabh Kulkarni (Siemens)\n---------------------\nRoutability Optimizing Me
 thodology Using Flexible Pin\n\nWe introduce a new design method to optimi
 ze routability through flexible pin.\nIt contributes to securing routing r
 esources for the entire block by using flexible pins, which provide multip
 le pin‑access points on the highly congested lower metal layers of advance
 d node technologies, together w...\n\n\nJinman Kang, Chaewon Song, Heeyoun
 g Moon, Sangdo Park, Jun Seomun, and Hyung-Ock Kim (Samsung Electronics)\n
 ---------------------\nXChip: A Guardrailed Agentic Gen-AI Front-End Flow 
 from Intent to GDSII\n\nModern chip design teams are increasingly explorin
 g Gen-AI to improve productivity in front-end design, yet practical adopti
 on remains challenging. Most existing Gen-AI tools focus on code generatio
 n or downstream assistance, while critical front-end tasks before RTL, suc
 h as system partitioning, in...\n\n\nKaiyuan Yang, Tiantai Deng, Charith A
 bhayaratne, and John Goodenough (University of Sheffield)\n---------------
 ------\nAn Adaptive Dynamic Power Reduction Technique for Digital Filters\
 n\nDigital FIR filters are typically designed for worst-case full-scale in
 put precision, resulting in unnecessary dynamic power dissipation when pro
 cessing low-amplitude signals. This paper introduces an adaptive technique
  that tracks real-time signal dynamic range and selectively disables toggl
 ing of ...\n\n\nAnkur Bal and Prince Bansal (STMicroelectronics) and Harvi
 nder Singh (Synopsys)\n---------------------\nAgentic AI Partition And Flo
 orplan Assistance For PCIe/CXL Subsystem Physical Design\n\nThe deployment
  of advanced high-speed protocols (e.g., PCIe Gen6/CXL) in multi-billion-g
 ate designs creates a severe "Logical-Physical Gap," where traditional imp
 lementation flows suffer from unmanageable runtimes and convergence volati
 lity. This work introduces a novel Cognitive Agentic Framework t...\n\n\ny
 uwenyuan gao (Cadence Design Systems, Inc.)\n---------------------\nNovel 
 methodology to replace OpenAccess inputs for hierarchical chip constructio
 n\n\nState-of-the-art microprocessors become more complex with every gener
 ation. Therefore, large microprocessor designs are implemented hierarchica
 lly. For Physical Design this means smaller building blocks are being proc
 essed from RTL to GDS first. Following, these pre-built blocks can be inte
 grated at...\n\n\nEduard Herkel, Jesse Surprise, Joel Earl, and Gregory Sc
 haeffer (IBM Research)\n---------------------\nNovel methodology for in co
 ntext blockage modification for high-speed global clock routing\n\nModern 
 microprocessors grow increasingly complex with each generation, making hie
 rarchical design essential for managing scale and complexity. In Physical 
 Design, this translates into processing smaller building blocks from RTL t
 o GDS, which are later integrated at higher levels. A critical aspect i...
 \n\n\nJonas Oberröhrmann, Jan Himanek, Eduard Herkel, and Peter Nasveschu
 k (IBM Research)\n---------------------\nPlug-and-Verify Using Real USB De
 vices for Front-End Host DUT RTL Validation\n\nFront-end verification of c
 omplex SoCs requires realistic stimulus to validate protocol compliance an
 d system-level functionality early in the design cycle. Traditional transa
 ction-based verification methodologies rely on virtual transactors and ext
 ensive software testbenches to emulate peripheral b...\n\n\nSuchir Gupta (
 Synopsys)\n---------------------\nA Hybrid Simulation and Formal Verificat
 ion Approach for Exhaustive Interrupt and Status Flag Verification\n\nVeri
 fication of status flags and interrupts is critical for correct interactio
 n between IP components, yet exhaustive validation of interrupt behavior r
 emains challenging when relying solely on simulation-based approaches. Thi
 s approach presents a hybrid simulation and formal verification methodolog
 ...\n\n\nGiovanni Auditore, Jagriti Khurana, Shaifali Bansal, and Vikas Sa
 urav (STMicroelectronics) and Archana Arya (ST Microelectronics)\n--------
 -------------\nCognitively Guided EM-Aware Routing Approach for Efficient 
 Layout Implementation\n\nElectromigration (EM) and resistance constraints 
 are traditionally verified at sign-off, making routing electrically blind 
 and leading to costly post-layout iterations. This paper introduces a simu
 lation-driven routing (SDR) methodology that integrates electrical intent 
 into the layout process, enab...\n\n\nAkshita Bansal and Sachin Bhasin (Ca
 dence Design Systems, Inc.) and Rajeev Singh and Nisha Rana (STMicroelectr
 onics)\n---------------------\nAutomotive Logic Test Power Management\n\nT
 est coverage, test time, and test power are tradeoff on automotive system 
 logic test. Unlike test coverage and test time, power is critical factor w
 hich is hard to be predicted and evaluated when implementation. Logic test
  usually has large amount of registers toggled at the same time and result
 s i...\n\n\nChen Yuan Kao, Ming Hsien Hsiao, Sin Huei Li, and Chen Tsai We
 i (Global Unichip)\n---------------------\nFully Automated On‑Chip Inducto
 r Synthesis for High‑Frequency VCO with ML based Optimization flow\n\nDesi
 gning passive components for RF and high-speed ICs at advanced nodes prese
 nts significant challenges: manual layout creation, complex DRC compliance
 , fragmented flows, and limited early accuracy due to lumped models. These
  issues lead to long iterations, manual S-parameter handling, and increase
 ...\n\n\nSahil Jha, Kapil Tyagi, Nitin Jain, and Atul Bhargava (STMicroele
 ctronics) and Prayes Jain and Vishesh Kumar (Cadence Design Systems, Inc.)
 \n---------------------\nLibrary PPA DTCO with Library Profiler\n\nStandar
 d cell technology is advancing rapidly, with each new generation introduci
 ng greater complexity and heightened design challenges. As designs evolve,
  meeting critical design goals across new processes becomes increasingly d
 emanding, making Design-Technology Co-Optimization (DTCO) more importan...
 \n\n\nJaehwan Jeon, Inguk Min, Ilsu Son, and Byungsu Kim (Samsung Electron
 ics) and Ahyoung Kwak and Connor Schentag (Siemens)\n---------------------
 \nEfficient Power Management in USB4 Routers\n\nEfficient power management
  is essential to address the growing demand for low-power connectivity sol
 utions. It aligns with mobile compute, always on, and compute everywhere i
 nitiatives, offering increased battery lifetime, and strengthens the compe
 titiveness of our IPs. We have developed an innovati...\n\n\nScott Guo, Ju
 njun Liang, Jack Deng, Hongwei Ma, Fei Ren, and Morten Christiansen (Synop
 sys)\n---------------------\nLow power optimization through fast and accur
 ate time-based power analysis\n\nThis paper introduces a low power optimiz
 ation flow based on time-driven power analysis to reduce dynamic power. Ou
 r approach is to integrate simulation-based toggle rate estimation, which 
 was not actually introduced into commercial tools due to runtime and limit
 ed input vectors despite high accurac...\n\n\nSORA PARK, MYUNGJIN CHOI, HE
 ONSEOK HONG, JONGPIL LEE, and KIJOON HONG (Samsung Electronics) and NAYEON
  PARK, KUNSANG PARK, HYESUN KIM, and JONGWON YI (Synopsys)\n--------------
 -------\nMulti-Cycle Dynamic Vectorless Analysis for Improved PDN Signoff\
 n\nThe exponential growth of neural network architectures targeting human-
 level intelligence has driven the development of hyperscale, transformer-b
 ased AI accelerators, with training requirements reaching up to 8 × 10^23 
 floating-point operations (FLOPs). This has introduced extreme computation
 al dema...\n\n\nMahesh Yatagiri (Qualcomm); Chen Li, Nikhil Jatana, and Ma
 hesh Subramanian (Cadence Design Systems, Inc.); and Palkesh Jain and Anuk
 ul Rangarajan (Qualcomm)\n---------------------\nEnhancing the Robustness 
 of Impinj RAIN RFID Design through the Application of AI-powered Process F
 low\n\nUHF RFID tagging is the fastest-growing segment of the RFID market,
  connecting billions of items worldwide. By enabling internet connectivity
  and real-time visibility into everyday objects—such as apparel, medical s
 upplies, automotive parts, and food—Impinj RAIN RFID facilitates truly sca
 lable Inter...\n\n\nMan Chun Liu, Agustinus Sutandi, Eric Wong, and Howard
  Tang (Impinj) and Devdatt Haldipur and Lih-Jen Hou (Siemens)\n-----------
 ----------\nA Chip-Level DTCO Framework for Yield-Aware Back-End Design: L
 ayout-Aware Misalignment Correction in DRAM\n\nWe propose a chip-level, la
 yout-aware DTCO framework to correct deterministic interlayer misalignment
 . Using layout-driven features and machine learning, the proposed approach
  achieves ~70% variation reduction, enables fast inline prediction, and im
 proves yield on silicon-proven products.\n\n\nHyeJin Kim (Samsung Electron
 ics) and SoYoung Kim (Sungkyunkwan University)\n---------------------\nAcc
 elerating IR and Timing Convergence with Revolutionary IR-ECO\n\nComplex a
 pplications (such as AI & HPC) and advanced tech nodes are driving a drama
 tic increase in design scale and complexity. It's currently impractical to
  construct a robust power delivery network (PDN) by consuming a large amou
 nt of design resources and the higher local cell density causes worse...\n
 \n\nPing Ding, Tuo Wang, and Guohua Zhou (Sanechips) and Li Zou and Chang 
 Zhao (Synopsys)\n---------------------\nA Novel Design Approach for Optimi
 zed EMC and Thermal Performance in Next-Generation Automotive Applications
 \n\nWith the ongoing advancement of automotive intelligence, vehicles are 
 incorporating an increasing number of semiconductor chips to improve effic
 iency and functionality. This technological progression results in elevate
 d current levels across automotive systems, leading to two key physical ch
 allenges...\n\n\nTakuya Suzuki (DENSO) and Lih-Jen Hou and YuLing Lin (Sie
 mens)\n---------------------\nBeyond Scripting: API Based HDL Generation\n
 \nLooking at the block diagram of any modern SoC – whether a standalone de
 vice or a chiplet – and you will see that most of the blocks, and die area
 , consists of generated logic. From regular structures like RAMs and ROMs,
  to semi-regular structures like control/status register and NoCs, to enti
 re pro...\n\n\nJack Greenbaum (INTEGRITY Security Services)\n-------------
 --------\nIdentifying Weakest Links: A Cell Scoring Metric for Robust Desi
 gn in Advanced Nodes\n\nAdvanced-node standard cell libraries often includ
 e thousands of cells characterized across 50+ PVT corners. \n\nIdentifying
  high-risk cells, those most prone to LVF variation or exhibiting abnormal
  trends across drive strength, VT, or gate length, is critical for:\n- Gui
 ding PnR and STA tools to apply...\n\n\nsanthosh kamatam and Pramod Gayakw
 ad (NXP) and Ajay Kumar, Ray Valencia, and Gabriel Rojas (Siemens)\n------
 ---------------\nPerformance Boosting DTCO Methodology for 1-to-1 Metal-Ga
 te Pitch Ratio\n\nWe addressed 1:1 GR Tech. challenges, Maximize pros and 
 Minimize cons. In this work, we proposed 1) DR/PDN optimization to minimiz
 e the loss of routing resource by increasing routability through the metho
 d of getting more pin points and better pin connection. Also, we proposed 
 2) enhanced design flo...\n\n\nTaeyong Bae (Samsung Electronics)\n--------
 -------------\nToward an Open Chiplet Ecosystem: Arm® Foundation Chiplet S
 ystem Architecture\n\nThe rapid growth of AI workloads is fundamentally re
 shaping system-on-chip (SoC) design. Monolithic scaling is increasingly co
 nstrained by reticle limits, rising costs, power density, and yield challe
 nges, while AI systems demand heterogeneous compute, high-bandwidth memory
 , and system-level co-desi...\n\n\nShivangi Agrawal and Rohit Gupta (ARM)\
 n---------------------\nAccelerating DFT Verification and Enhancing Debugg
 ability Using Veloce-Based Full Chip Gate-Level Emulation\n\nThis paper de
 scribes the development of a full-chip gate-level emulation environment th
 at enables DFT verification and the successful application of Debug STIL v
 ectors generated by the Tessent DFT tool in the Veloce emulation environme
 nt, significantly improving debuggability and shortening the prod...\n\n\n
 Jaesung Park (Samsung Electronics); Jeongjun Lee (Siemens); Hyundon Kim, K
 youngmin Park, Youngsik Kim, Dohyeon Lee, Younghyun Cho, Changkyu Lee, and
  Byungjik Kim (Samsung Electronics); and Inhwan Kim, Justin Lee, and Chanj
 in Kim (Siemens)\n---------------------\nARTEMIS: Agentic AI for EDA\n\nFr
 ont-end RTL verification workflows consume significant compute resources a
 nd engineer time, with Verilog simulations often failing due to syntax err
 ors, testbench issues, or configuration problems detected only after resou
 rce consumption. Traditional workflow management lacks predictive intellig
 en...\n\n\nFelix David, Dhara Vaishnav, Nupur Bhonge, and Sameer Farooq (A
 WS)\n---------------------\nNovel approach to signoff large MRAM memory IP
  using Hierarchical flow\n\nAt SOC level, customer requires comprehensive 
 electrical views, of the memory IP we design, to support Power and Reliabi
 lity sign-off. Generating APL models requires waveform database (FSDB) fro
 m the spice simulation of the IP.  As IP size is very huge, full extracted
  macro simulations are not pract...\n\n\nDinesh Chandra, Sushma Sambtur, D
 eepak Kumar Sahoo, and Kumari Saumya Diwedi (GlobalFoundries) and Naveen B
  and Shreya Sashi (Synopsys)\n---------------------\nAI-Driven Co-Optimiza
 tion of Power Delivery Network for High-Power Cores in 2.5D Advanced Packa
 ging\n\nThe increasing adoption of chiplet-based 2.5D advanced packaging h
 as introduced formidable power integrity (PI) challenges, requiring the si
 multaneous optimization of static DC performance and dynamic AC response—a
  complex, multi-variable task traditionally reliant on manual expertise. T
 his paper pr...\n\n\nShineng Ma (Sanechips), Li Zou (Synopsys), and Bin Yu
  (Sanechips)\n---------------------\nChannel Width Optimization for IR Dro
 p Reduction in Advanced SoCs\n\nPower delivery challenges in advanced Syst
 em-on-Chip (SoC) designs are increasingly critical due to stringent perfor
 mance, area, and reliability requirements. Traditional approaches to chann
 el width optimization are performed late in the design cycle, often relyin
 g on post-RTL Engineering Change Ord...\n\n\nShashank NA, Govind Pal, and 
 Shreyasi Dastidar (STMicroelectronics) and Prateek Gupta, Amit Jangra, Awa
 ntika Singh, and Krish Aggarwal (Synopsys)\n---------------------\nFrom Co
 ncept to PPA Confidence - Methodology for rapid RTL evaluation and signoff
  with Joules RTL Design Studio.\n\nProviding accurate Power, Performance, 
 and Area (PPA) feedback for RTL changes in conventional RTL-to-GDS flows i
 s slow and resource-intensive, often taking 5-7 days for 2-3M instance blo
 ck-level runs. This process requires significant compute resources, extens
 ive cross-team coordination, and lacks ...\n\n\nNimish Agashiwala (Cadence
  Design Systems, Inc.)\n---------------------\nAn Optimized Full-Chip Anal
 og Mixed-Signal (AMS) Verification Approach for PVT Calibration in FPGA Sy
 stems\n\nMicrochip FPGAs feature multiple I/O banks, each configurable ind
 ependently for diverse standards such as SSTL, LVSTL etc., enabling design
 ers to mix and match signaling protocols across the same device while cove
 ring a wide frequency range. I/O banks support voltages from 0.5V to 3.3 V
 , inclu...\n\n\nShubhi Agrawal, Ramteja Kothamasu, and Prajjwal Soni (Micr
 ochip) and Neel Natekar and Harshit Arora (Siemens)\n---------------------
 \nIntegrated Design Approach for Robust and Area-Efficient IO Ring in Adva
 nced Process Nodes\n\nIn advanced semiconductor technology nodes, designin
 g a robust and area efficient I/O ring poses significant challenges due to
  tighter design margins, increased integration density, and stringent reli
 ability requirements. To cultivate this efficiency requires a methodology 
 for high performance and r...\n\n\nSukhmani Virk, Ninad Khire, Kavithaa Ra
 jagopalan, Sneha Shetty, and Siddharth Gupta (Texas Instruments (TI))\n---
 ------------------\nAI-Enabled Flow for Silicon Area Reduction and Design 
 Closure\n\nAbstract—Artificial Intelligence (AI) has emerged as a transfor
 -\nmative technology in electronic design automation (EDA) flows,\nenablin
 g significant improvements in power, performance, and\narea (PPA) metrics.
  This paper explores the critical role of AI-\ndriven techniques in optimi
 zing semiconductor ...\n\n\nsaurabh gautam and anil yadav (STMicroelectron
 ics)\n---------------------\nFrom Broken Regression to Root-Cause Commit i
 n One Click A Two-Stage Regression-Aware Git-Bisect Framework for Large-Sc
 ale Hardware Verification\n\nLarge-scale hardware verification relies on m
 assive regression testing across thousands of tests, seeds, and configurat
 ions. When a previously passing regression begins to fail, identifying the
  exact code change that introduced the failure is extremely difficult due 
 to non-determinism, merge commits...\n\n\nSai Sri Ram Goud Chamakuri (Cade
 nce Design Systems, Inc.)\n---------------------\nA Novel Methodology for 
 Automated LVS Rule Deck Verification: Truth Table and Device Extraction Qu
 alification\n\nModern semiconductor fabrication faces an escalating verifi
 cation challenge as technology nodes shrink to 3nm and beyond, where Layou
 t Versus Schematic (LVS) verification complexity has grown exponentially. 
 Today's LVS must go beyond comparing Schematic and Layout designs; it must
  extract R/C values...\n\n\nAhmed Saleh (Siemens); Jaeyoung So, Minho Jung
 , Heejae Lim, Jimin Yeo, Yunseong Lee, and Jiyoung Shin (Samsung Electroni
 cs); and Mohamed Alimam (Siemens)\n---------------------\nAI&Cell based An
 alog Circuit Topology Generator(CTGEN)\n\nThis provides the new analog des
 ign methodology which will generates schematic topology for practical usag
 e.\nThe abstract concept of topology generation is following.\nDecompose t
 he many circuits schematic resources to small cells or blocks.\nThen const
 ruct for the best combination topology to meet th...\n\n\nAkira KURUSU, Ko
 uji HIRAI, Shigeya YAMAGUCHI, Jin WATANABE, Takuto OGURA, Chao GENG, Masan
 ori KUSANO, Ryou HAMADA, Kazuhiro KUDO, and Nobuto ono (Jedat Inc.); Tsuyo
 shi MASUBUCHI and Nobukazu TAKAI (Kyoto Institute of Technology); Shigetos
 hi NAKATAKE (University of Kitakyushu); and Tetsuya IIZUKA (The University
  of Tokyo)\n---------------------\nAutomating DFT Intelligence: Addressing
  TCPF HotSpots at Source through Design Aware Test Points in SystemRDL-to-
 RTL Generators\n\nAs SoC complexity scales, the resulting explosion in Aut
 omatic Test Pattern Generation (ATPG) pattern counts has become a primary 
 driver of escalating manufacturing test costs. A critical bottleneck in th
 is process is the emergence of "TCPF (Test cost Per Fault) Hotspots" acros
 s designs such as high...\n\n\nVeerabhadrarao Vasa and Rajesh Gottumukkala
  (Google) and Vikash Gupta and Freddy Nunez (Agnisys)\n-------------------
 --\nAn Adjustable Length Compression Method for MBIST Repair Information\n
 \nEmbedded memories occupy the largest part of modern SoCs. As memories ar
 e high-density physical structure, they are more prone to failures than ot
 her circuits and concentrate the large majority of fabrication faults, aff
 ecting yield adversely. Hence, memory Built-In Self-Repair(BISR) is mandat
 ory fo...\n\n\nOuyang Keqing, Qi Cheng, Minqiang Peng, and Guohua Zhou (Sa
 nechips) and Sri Ganta (Synopsys)\n---------------------\nScalable, Protoc
 ol-Agnostic Clockless In-Band Reset Architecture for Serial Link IPs in Mu
 lti-Domain SoCs\n\nModern multi-domain SoCs almost always integrate serial
  link IPs, making reliable system reset a critical challenge, especially w
 hen clock generation circuitry is compromised. Conventional out-of-band re
 set schemes require dedicated pins, limiting scalability, while existing i
 n-band reset solutions ...\n\n\nAradhana Kumari and Ankur Bal (STMicroelec
 tronics)\n---------------------\nNo Credit Where Credit Is Due: Quiesced F
 ormal Check for PCIe Crediting\n\nPCIe Gen6/7 introduces major architectur
 al enhancements to meet the bandwidth and latency demands of AI and datace
 ntre workloads. Bandwidth doubles from 32 GT/s to 64 GT/s to 128GT/s throu
 gh support for PAM4 signalling, flit‑based transfers, and multiple virtual
  channels (VCs). These capabilit...\n\n\nIsha Lale, Pradip Prajapati, and 
 Anshul Jain (Synopsys)\n---------------------\nModeling and Optimization o
 f Power MOSFET Device Layouts with optiSLang Tool\n\nThe performance of la
 rge semiconductor devices, such as power MOSFETS that carry large currents
 , depends not only on their size or area but also their layout and package
  implementation choices. Factors such as device aspect ratios, metal routi
 ng strategies and pad locations influence current flow th...\n\n\nMandar D
 eshpande and Claudia Dumitrescu (Microchip) and Khawja Sikander (Synopsys)
 \n---------------------\nMulti-Cycle Interconnect Synthesis in Small to La
 rge Cutting Methodology\n\nThe IBM Small to Large (S2L) methodology is a f
 low that transitions flat small block physical design models to abutted la
 rge block models.  One of the biggest challenges in the S2L flow has been 
 latch tree optimization.  Latch trees are fully described in the input log
 ic, so design changes often req...\n\n\nJesse Surprise, nancy Zhou, Chandl
 er Brown, and Josiah Hamilton (IBM Research)\n---------------------\nDeep 
 Reinforcement Learning Paradigm for Analog Design Automation\n\nWe propose
  a tool capable of Automating Analog Design Sizing at scale in an industri
 al setting that meets sign-off quality. There have been several academic p
 apers which talk about optimizing analog circuit but most of them operate 
 under the academic umbrella which prohibits them from being viable s...\n\
 n\nSharath C R, Senthil Kumar Sundaramoorthy, Krishna Teja, Chanakya K V, 
 Sujith M A, and Suberus Heartrisha (Texas Instruments)\n------------------
 ---\nAI-Assisted EDA Tools Development\n\nEDA tool development often suffe
 rs from redundant effort and complexity due to repeated implementation of 
 common HDL parsing and construction tasks. This work introduces an AI-assi
 sted framework that leverages MCP modular building blocks and an Agentic A
 I approach to automate tool generation, elimin...\n\n\nMaya Safieddine, Ar
 vind Haran, Richard Carbone, Kenneth Poor, Faith Curtis, Ali El-Zein, and 
 Viresh Paruthi (IBM Research)\n---------------------\nCustom Implementatio
 n of High-Speed Digital Blocks using Virtuoso Studio\n\nHigh-speed digital
  blocks integrated within traditional Place & Route flows pose verificatio
 n and implementation challenges that analog-centric methodologies cannot f
 ully address. As process technologies scale and timing margins shrink, the
 se blocks exhibit strong sensitivity to parasitics, layout-d...\n\n\nPrati
 k Korde and Sumanth S (Cadence Design Systems, Inc.) and Kishan Chanumolu 
 (Micron)\n---------------------\nBIMEM-RAG: Reinforced Dual Memory Retriev
 al with Bidirectional Reasoning for RTL Synthesis and Summarization\n\nAut
 omating Register-Transfer Level (RTL) code generation and summarization is
  critical for improving hardware design productivity and reducing time-to-
 market. However, existing approaches struggle due to limited Verilog and V
 HDL training data and the structural concurrency inherent in hardware desc
 r...\n\n\nPrashanth Vijayaraghavan, Luyao Shi, Apoorva Nitsure, David Beym
 er, Ehsan Degan, and Vandana Mukherjee (IBM Research)\n-------------------
 --\nCorrect-by-Construction Framework for Robustness Against Divergent Vol
 tage Drops and High Clock Divergence\n\nLimitations in Sign-off Methodolog
 y:\nTraditional STA corner selection 10% lower STA corner from PMIC voltag
 e is selected-  design is constantly optimised for 10% lower voltage, ther
 eby failing to build margin against differential drop.\nIR aware STA does 
 not account timing path's geometric imbalances...\n\n\nPRATEEK PENDYALA an
 d Mathew Kaipanatu (Google)\n---------------------\nAccelerating Formal Cl
 osure on Complex Hardware Designs via AI-Driven Helper Generation\n\nAs ha
 rdware designs grow in complexity, Formal Verification (FV) often hits sca
 lability walls, resulting in "bounded" proofs rather than full closure.Dee
 p state-space exploration is limited by computational resources. Overcomin
 g this typically requires "helper" assertions (invariants), but manually .
 ..\n\n\nBindumadhava Singanamalli and Pandithurai Sangaiyah (Google) and S
 ean Safarpour, Sayandeep Sayandeep Sanyal, Sandeep Jana, and Raja Mahadeva
 n (Synopsys)\n---------------------\nMulti-Level Intelligent Waveform Orch
 estration: Specification-Aware Framework for Eliminating Storage-Debug Tra
 deoffs\n\nTraditional FSDB (Fast Signal Database) capture forces verificat
 ion teams into an impossible choice: capture everything and face unsustain
 able storage costs, or capture selectively and risk missing critical debug
  data. We present a three-tier intelligent framework with live dashboard t
 hat eliminates...\n\n\nVinoth Selvan (NVIDIA)\n---------------------\nEnab
 ling AI Agent Flows for Verification Triage & Debug\n\nVerification remain
 s the most time-consuming phase of hardware development, with millions of 
 simulation jobs generating diverse fail signatures. Manual triage and root
  cause analysis (RCA) of these failures is a critical bottleneck, consumin
 g significant engineering effort and requiring specialized ...\n\n\nArvind
  Haran, Bryan Hickerson, Divya Joshi, Yugal Kithany, Kenny Poor, Maya Safi
 eddine, Ali El-Zein, Viresh Paruthi, and Daniel Coops (IBM Research)\n----
 -----------------\nGraph Isomorphism for Explainable Transistor-level Circ
 uit Comparison\n\nCircuit comparison is a fundamental task to determine wh
 ether two circuit representations are structurally and electrically equiva
 lent. Modern EDA flows frequently introduce renaming, reordering, and symm
 etry-preserving transformations even when functionality is unchanged. Exis
 ting pattern-matching ...\n\n\nAshutosh Jadhav, Xin Zhao, Ehsan Degan, and
  Vandana Mukherjee (IBM Research)\n---------------------\nTaming the Beast
 : A Formal Verification Approach to Solve Design Complexity- GPU Compressi
 on Block Case Study\n\nFormal verification plays a critical role in modern
  hardware development by delivering exhaustive, mathematically rigorous va
 lidation to ensure functional correctness. As digital architectures scale 
 in complexity—driven by advanced features and the growing demand for AI ce
 ntric workloads—formal veri...\n\n\nUsha Rani Bagadi, Rahul Dabur, Namita 
 Rawat, and Bathri Narayanan Subramanian (Intel)\n---------------------\nAr
 chitectural Formal Verification of Configurable Address Translation Logic 
 for early bug exposers\n\nHighly configurable, hash‑based address translat
 ion logic is central to modern memory subsystems, enabling scalability, pa
 rallelism, and load balancing(fairness) across multiple clients and lanes.
  However, the resulting configuration and address spaces grow far beyond w
 hat simulation can feasi...\n\n\nMohit Choradia, Suraj Kamble, and Winnie 
 Yeung (Microsoft)\n---------------------\nMulti-Agent Generative AI Pipeli
 ne for assisting in Design Verification\n\nSecure Multi-Agent Generative A
 I Pipeline for Context-Aware Design Verification\n\nThe escalating complex
 ity of modern System-on-Chip (SoC) designs has relegated approximately 70%
  of the total design cycle to functional verification. This critical phase
  is currently plagued by knowledge fragmentation,...\n\n\nPratham Gowtham,
  Tejas Bhat, Chethan Bomanna, and Anil Deshpande (Samsung Electronics)\n--
 -------------------\nAuto-Chk: Closing the Last-Mile Interpretation Gap in
  Digital Sign-off via a Neuro-Symbolic Compiler Framework\n\nRecent RCA st
 udies show that failures in digital sign-off rarely stem from EDA executio
 n itself, but from the last-mile interpretation layer. Script-based automa
 tion, built on rigid syntax matching, breaks under tool/version drift and 
 cannot enforce cross-stage causality, leading to silent misses. H...\n\n\n
 Wentao Dai (Cadence Design Systems, Inc.)\n---------------------\nA Progra
 mmable, Synthesizable CMOS Analog Optimization IP Core for Real-Time Contr
 ol\n\nThis work presents an automated EDA toolchain for synthesizing progr
 ammable and scalable CMOS analog optimization IP cores. Addressing the lat
 ency wall in real-time control, where conventional digital solvers face po
 lynomial scaling bottlenecks, our methodology translates high-level mathem
 atical spe...\n\n\nPriyanshu Sahu, Swapnil Sharma, Sachin Khoja, and Palak
  Jain (Vellex Computing) and Jason Poon (Cal Poly, San Luis Obispo)\n-----
 ----------------\nANA-MODELGEN: Automating Analog IP Model Generation and 
 Validation for Efficient Mixed-Signal Verification\n\nAnalog IP verificati
 on remains a bottleneck in modern mixed-signal SoC development  due to len
 gthy SPICE simulation times and integration challenges. This paper introdu
 ces  ANA-MODELGEN, a comprehensive hierarchical modeling methodology that 
 transforms analog IP verification through automated model ...\n\n\nAadhar 
 Sharma (Texas Instruments (TI)); Parthasarthy Ramesh, Rinu Mathew, and Dav
 id Mendoza (Texas Instruments); Sooraj Sekhar (Texas Instruments (TI)); an
 d Srijan Soni (Texas Instruments)\n---------------------\nEfficient power 
 modeling of multi-domain clock gating circuits\n\nStandard LCBs (Local Clo
 ck Buffers) drive a single clock gating domain and are controlled by a sin
 gle clock enable signal. Even for smaller domains, the same LCB is used fo
 r clock gating, leading to a large number of under-loaded LCBs. Multi-doma
 in clock gating circuits (or Micro Clock Gated, MCG) w...\n\n\nSpandana R,
  Nagu Dhanwada, and Wesley Dungan (IBM Research)\n---------------------\nA
  Distributed and Scalable Dynamic Power Integrity Flow from Early Analysis
  to Sign-off for Large-Scale SerDes Designs\n\nFor large-scale SerDes desi
 gns, dynamic power integrity sign-off is becoming increasingly challenging
  due to growing design scale and performance demands. Modern SerDes integr
 ate analog blocks, digital blocks, sensitive clocks, decaps with complex P
 ower Delivery Network (PDN) design. Such designs ca...\n\n\nXin Shu, Jinro
 ng Yan, Hang Sun, Xuewei Ding, and Xiaofan Lu (Sanechips Technology Co.,Lt
 d) and Xiaomei You and Jie Cheng (Synopsys)\n---------------------\nAccura
 te Impact Modeling for Threshold Voltage  Mismatch of Transistors in Same 
 Chip\n\nIt has been observed for several years that transistors of differe
 nt threshold voltage types (VT) in one chip may contain different silicon 
 to SPICE gap (S2S). This gap may result in risk of yield loss when industr
 y uses SS (all VTs at SS) and FF (all VTs at FF) in signoff because of omi
 tting risk w...\n\n\nShih-Jie Chang, Yen-Pin Chen, Tzu-Hen Lin, and Florin
  Dartu (TSMC)\n---------------------\nHardening Security of HW IPs by Veri
 fying Their Negative Space Formally\n\nNegative space verification is cruc
 ial for hardware security: inputs that are invalid or unexpected can trigg
 er silent and delayed failures that designers often treat as "don't care".
  These failures. If exploitable, can cause security issues. We show that u
 nlike software fuzzing, formal verification...\n\n\nSayak Ray, Jason Fung,
  Bo-Yuan Huang, Arun Kanuparthi, Mohammad Bidmeshki, Mehdi Mohtashemi, Ram
 ya Hariharan, and Vivek Tiwari (Intel)\n---------------------\nWeeding Out
  Timing Gaps and Improving Performance of DDR Controllers Using Formal Ver
 ification\n\nLPDDR6 delivers substantial gains in bandwidth, power efficie
 ncy, and scalability through phase‑aware command scheduling, multi‑sub‑cha
 nnel architectures, and data rates reaching 12.8 GT/s. These architectural
  innovations significantly complicate the verification of minimum t...\n\n
 \nRaushan Kumar and Anshul Jain (Synopsys)\n---------------------\nFormall
 y Validating Industry Standard BCH‑ECC/CRC Codes – A Step by Step Recipe\n
 \nFormal verification of CRC and ECC hardware does not scale with conventi
 onal techniques due to large Datapath's, extensive lookup tables, and comp
 lex Galois-field arithmetic. Existing approaches rely on monolithic end-to
 -end properties, bounded proofs, or coarse linearity abstractions, and eve
 n then...\n\n\nDisha Puri and Aatreyi Bal (Synopsys)\n--------------------
 -\nBreaking Sequential Depth Barriers: An FSM-Driven Bridge for the Formal
  Verification of Virtually Address-Mapped Hardware Registers\n\nThis paper
  presents the formal verification of a subsystem with indirect read mechan
 isms and a nonstandard access protocol. Verifying registers using the cont
 rol and status register (CSR) protocol typically requires a proof accelera
 tor to convert a standard bus into the CSR protocol. However, this s...\n\
 n\nSarvesh TIWARI, Ayush ., and Ashwin Singhal (STMicroelectronics) and To
 m Weiss and Erik Seligman (Cadence Design Systems, Inc.)\n----------------
 -----\nHierarchical Functional Fault Grading with Auto-Identification of O
 bservation Points for Faster Fault Coverage closer in Complex SoCs\n\nAs S
 ystem-on-Chip (SoC) designs transition toward massive scale and multi-die 
 architectures, achieving near-zero Defective Parts Per Million (DPPM) is i
 ncreasingly hampered by the limitations of traditional structural Design-f
 or-Test (DFT). Scan-based testing frequently leaves critical coverage gaps
 ...\n\n\nVeerabhadrarao Vasa, Rajesh Gottumukkala, Kasi Chunduri, and Kart
 hikeyan Subramanian (Google) and Arun Gogineni and Gaurav Goel (Siemens)\n
 ---------------------\nAccurate Full-Custom Thermal and EM Analysis for Ad
 vanced Nodes\n\nAnalyzing circuits for susceptibility to electro-migration
  has been a requirement for integrated circuit design since the 1960's.  I
 n fact, one of the basic equations for electro-migration, Black's Equation
 , was formalized in 1969 and is still in use today. In related work, Stati
 stical Electro-migra...\n\n\nDavid Newmark (Advanced Micro Devices (AMD))\
 n---------------------\nFlexible & Scalable Network Modeling for AI/HPC Ne
 twork Verification\n\nValidating high-performance AI/HPC network designs p
 resents significant challenges, particularly when verifying multi-path fea
 tures like ECMP and congestion control that standard Point-to-Point (P2P) 
 environments cannot adequately cover. We propose a comprehensive, SystemVe
 rilog/UVM-based network mo...\n\n\nSanghyeon Hwang and Minho Chu (MangoBoo
 st)\n---------------------\nA Hybrid SRAM-DRAM Memory Architecture for Ult
 ra-Low-Power Wakeup in SoCs\n\nPower consumption plays a key factor in SoC
 . With advances made in wireless technologies through 3GPP LTE & NR, IEEE 
 Wifi and now with 3GPP 6G, there is a need for advanced architecture in So
 C. Typically, a SoC uses sleep and wakeup (warmboot) procedure for saving 
 battery. The warmboot procedure inv...\n\n\nPrasad Dandra (Samsung Electro
 nics); Thejeswara Reddy (Samsung); Tushar Vrind and Somraj Mani (Samsung E
 lectronics); and Venkata Raju Indukuri, Krishnakant Patil, and Amol Kumar 
 Jagtap (Samsung)\n---------------------\nOutsmarting State Space Complexit
 y through Proven Reset Abstraction Stratergies\n\nFormal verification rigo
 rously explores all possible system states, offering unmatched coverage an
 d the ability to detect subtle errors in complex designs. However, its exh
 austive nature leads to the state space explosion problem, making verifica
 tion computationally challenging. Reset abstraction mi...\n\n\nS R Pavitra
 , Sharika Shaju, and Anshul Jain (Synopsys)\n---------------------\nCost-B
 ased Partial Subgraph Matching for Circuit Pattern Recognition\n\nIdentify
 ing recurring sub-circuits within large transistor-level designs is a comm
 on requirement in circuit analysis and verification. Traditional approache
 s rely on exact subgraph isomorphism, requiring identical structure and at
 tributes between a pattern and a design. However, real designs often i...\
 n\n\nAshutosh Jadhav, Xin Zhao, Ehsan Degan, and Vandana Mukherjee (IBM Re
 search)\n---------------------\nAn AI-Enhanced Web-based Real-Time Analyti
 cs & Prediction Platform for ASIC Physical Design (PD) Flows\n\nAn AI-enha
 nced real-time analytics and prediction platform designed to bring compreh
 ensive intelligence to complex ASIC Physical Design (PD) flows. This tool 
 automatically captures PD runs, parses massive volumes of logs and reports
 , and unifies timing, congestion, CTS, IR/EM, DRC/LVS, runtime, and ...\n\
 n\nSubhash Uppala, Anoop Singh, Ayan Datta, and Manjunath Nayak (Sandisk)\
 n---------------------\nSigma Profiling: Profiling Solution for Power Inte
 grity Signoff\n\nSigma Profiling offers a breakthrough power integrity sig
 noff solution in chip design, overcoming coverage and runtime limitations 
 present in traditional dynamic IR analysis techniques. Conventional method
 s, such as peak power or tile-based cycle selection, often fail to compreh
 ensively capture high...\n\n\nGirish Deshpande, Anusha Vemuri, Vishal Mali
 k, Emmanuel Chao, and Santosh Santosh (NVIDIA) and Chidambaram Rakkappan, 
 Ayush Sood, and Tapas Govindraju (Synopsys)\n---------------------\nA Unif
 ied Silicon-Correlated Characterization Flow for High-PPA Standard Cell Li
 braries at Advance Nodes\n\nAdvanced‑node libraries must meet aggressive P
 PA targets across wide voltage ranges, including near‑/ultra‑low‑voltage o
 peration where process variation is amplified and non‑Gaussian. Traditiona
 l sensitivity‑based LVF (SBA) fails to retain accuracy under these con...\
 n\n\nPramod Gayakwad, santhosh kamatam, and Khushboo Rathore (NXP) and Raj
 esh Kotha (Synopsys)\n---------------------\nAgile Silicon: A GitOps-Based
  PD Orchestration Framework Enabling <10-Person PD Team to Deliver CPO Tap
 eouts\n\nCo-packaged optics (CPO) presents unique physical design challeng
 es: numerous small blocks with irregular shapes to accommodate photonics a
 nd analog integration, combined with frequent RTL changes extending close 
 to tapeout due to evolving system architectures of cutting-edge silicon ph
 otonics desig...\n\n\nRuosi Feng, Aadvivian Singh, Jonathan Elmhurst, and 
 Rishi Anand (Lightmatter Inc.)\n---------------------\nLLM-Aided Cell Clus
 tering for Placement Optimization of DRAM Peripheral Circuits\n\nPlacement
  quality strongly impacts routability and timing in DRAM peripheral circui
 ts. While expert designers manually identify structural patterns of cells 
 to be clustered during placement in small scale circuits to enhance the qu
 ality of results (QoR), this approach does not scale to large DRAM pe...\n
 \n\nSoyoon Choi, Chansol Hong, Jinyoung Lee, and Hyojin Choi (Samsung Elec
 tronics)\n---------------------\nOvercoming Accuracy and Scalability Limit
 s in Multi-Port On-Chip Electromagnetic Simulation Using a Hybrid Partial 
 Elements Equivalent Circuit Solver\n\nTraditional design cycles include mu
 ltiple tapeout and measurement cycles to achieve optimal performance.  Thi
 s increase in cost and delayed product introduction is no longer attractiv
 e with expensive advanced process nodes and working with condensed design 
 cycles.  Electromagnetic (Emag) simulation...\n\n\nAbishek Manian and Sona
 m Sadhukhan (Texas Instruments) and Garth Sundberg and Kelly Damalou (Syno
 psys)\n\nTopics: AI, Chiplet, Design, EDA, Quantum, Security, Systems
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