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DTSTAMP:20260730T152729Z
LOCATION:Seaside Ballroom B
DTSTART;TZID=America/Los_Angeles:20260728T133000
DTEND;TZID=America/Los_Angeles:20260728T140000
UID:dac_DAC 2026_sess289_ENGINV113@linklings.com
SUMMARY:Digitally Assisted Analog Techniques for Next‑Generation Data Conv
 erters, Test, and Clocking
DESCRIPTION:Ankur Bal (ST Microelectronics)\n\nOver the past two decades, 
 digital logic density has increased by more than three orders of magnitude
 , while analog metrics such as gain, linearity, and noise have improved on
 ly incrementally. Digital calibration and compensation can cut analog desi
 gn margins by up to 50%, enabling smaller and more power-efficient circuit
 s, while techniques such as dynamic voltage and frequency scaling, algorit
 hmic noise shaping, and digital redundancy consistently deliver order‑of‑m
 agnitude energy savings over analog-only solutions. Furthermore, digital s
 ubsystems inherently support in‑situ testability, with scan-based and BIST
  methods achieving production fault coverage exceeding 99%. Reflecting thi
 s shift, modern SoCs are now more than 80% digital—even in RF, clocking, a
 nd sensor interfaces. This talk explores how digitally assisted analog tec
 hniques are reshaping mixed‑signal design, enabling scalable, low-power, a
 nd highly testable solutions for next‑generation systems.\n\nTopics: AI, D
 esign, EDA\n\nSession Chair: Aishwarya Natarajan (HPE Labs)\n\n
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