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DTSTAMP:20260730T152730Z
LOCATION:Seaside RM 7
DTSTART;TZID=America/Los_Angeles:20260727T113000
DTEND;TZID=America/Los_Angeles:20260727T114500
UID:dac_DAC 2026_sess275_ENGPRES321@linklings.com
SUMMARY:A Probe-Based Time-Domain Methodology for Dynamic Thermal Manageme
 nt in Stacked-Die Architectures
DESCRIPTION:Sumanth Suraneni (Annapurna Labs US Inc.), Nikhil Jayakumar (A
 mazon), and Sujyesh Aanandh Manjunthan (Synopsys)\n\nDynamic Thermal Manag
 ement (DTM) techniques are increasingly critical for high-power heterogene
 ous chip designs, where sustained peak operation can lead to rapid thermal
  limit violations. We present a dynamic, probe-based thermal methodology t
 o quantitatively evaluate settling time post peak power events and maximiz
 e peak state duration. Design comprises of a compute die along with HBM pl
 aced on interposer and then package. Distinct tile based power map was cre
 ated for peak and lower activity (50-90%) states. Static thermal analysis 
 was performed to find the corresponding maximum temperatures.\nNext using 
 DTM analysis, the settling time was extracted, which is required for each 
 lower power state to reach steady-state temperature after exiting the peak
 . This was exponentially inverse to power. Lastly, peak state duration bet
 ween certain thresholds was maximized depending on the settling time of ea
 ch state. Maximum peak state duration of 80% and 76% were seen for peak to
  50% and 60% power states respectively. This methodology enables evaluatio
 n of transient metrics using DTM analysis by linking power throttling deci
 sions directly to time-domain thermal behavior, providing actionable insig
 hts for DVFS, workload scheduling, and safe peak performance budgeting.\n\
 nTopics: Chiplet, EDA\n\nSession Chair: Tim Helvey (Marvell)\n\n
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