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DTSTAMP:20260730T152729Z
LOCATION:Seaside RM 7
DTSTART;TZID=America/Los_Angeles:20260727T111500
DTEND;TZID=America/Los_Angeles:20260727T113000
UID:dac_DAC 2026_sess275_ENGPRES310@linklings.com
SUMMARY:Early Thermal Analysis and Silicon Correlation for Face-to-Face 3D
 IC Physical Design
DESCRIPTION:Jason Crop (Broadcom) and Sujyesh Aanandh Manjunthan (Synopsys
 )\n\nFace-to-face (F2F) 3DIC integration introduces new thermal challenges
  due to increased power density, inter-die heat coupling, and limited vert
 ical heat dissipation, making early thermal visibility critical during phy
 sical design. This work presents an early-stage thermal analysis methodolo
 gy jointly developed by the Synopsys RedHawk-ET team and the Broadcom APD 
 AI team to rapidly identify thermal hotspots in F2F 3DIC stackups. The pro
 posed flow leverages early floorplan and power information to enable fast 
 thermal evaluation, allowing designers to proactively adjust floorplanning
 , power distribution, or die placement to mitigate trapped heat. The metho
 dology is lightweight enough to execute in under a few hours, making it su
 itable for iterative use during early implementation stages. Correlation w
 ith post-silicon thermal measurements demonstrates prediction accuracy wit
 hin 3 °C across both top and bottom dice. This work highlights practical c
 onsiderations, tradeoffs, and lessons learned in deploying early thermal a
 nalysis as part of a production 3DIC physical design flow.\n\nTopics: Chip
 let, EDA\n\nSession Chair: Tim Helvey (Marvell)\n\n
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