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DTSTAMP:20260730T152649Z
LOCATION:Seaside RM 7
DTSTART;TZID=America/Los_Angeles:20260727T103000
DTEND;TZID=America/Los_Angeles:20260727T120000
UID:dac_DAC 2026_sess275@linklings.com
SUMMARY:Serving hot 3D-IC on clean and cool plates
DESCRIPTION:Explore key concepts that support connectivity, performance an
 d thermal management as 3D-ICs come into vogue for the next generation of 
 dense computation built on vertical stacking.\n\nComprehensive Physical Ve
 rification Approach for Heterogeneous 2.5/3D Integration\n\nAs semiconduct
 or technology advances, the industry is moving from traditional monolithic
  SoC designs to heterogeneous integration enabled by advanced 2.5D and 3D 
 IC packaging. These architectures deliver higher performance, improved pow
 er efficiency, and greater functionality by combining multiple d...\n\n\nN
 agaMalleswari Metla, Ravali Pagidooju, and KalyanaKumar Amruthuluri (Advan
 ced Micro Devices (AMD)) and Arman Davtyan, Sara Khalaf, and Baher El Saye
 d (Siemens)\n---------------------\nPhysical Signoff at Scale: Tackling TS
 V, Interposer, and ESD in 3DIC Systems\n\nThe proliferation of 3D Integrat
 ed Circuits (3DICs) and 2.5D chiplet-based architectures has introduced su
 bstantial complexity into physical signoff verification (PV) flows. These 
 advanced designs feature heterogeneous die stacking, multi-node integratio
 n, Through-Silicon Vias (TSVs), micro-bumps, a...\n\n\nMohannad Alshawi an
 d Qi Wang (Marvell)\n---------------------\nA Mixed-Domain Modeling Approa
 ch for Hatched Ground Planes in 3D Chiplet Die-to-die Interconnect\n\nThe 
 rapid growth of AI and machine-learning workloads has driven adoption of a
 dvanced packaging technologies such as silicon interposers, bridges, and h
 eterogeneous 3D integration in chiplet-based systems. These structures oft
 en require patterned ground planes, such as hatched or meshed geometries, 
 ...\n\n\nDr. Tim Wang Lee and HeeSoo Lee (Keysight Technologies) and Orlan
 do Bell (Giga Design Automation)\n---------------------\nEarly Thermal Ana
 lysis and Silicon Correlation for Face-to-Face 3DIC Physical Design\n\nFac
 e-to-face (F2F) 3DIC integration introduces new thermal challenges due to 
 increased power density, inter-die heat coupling, and limited vertical hea
 t dissipation, making early thermal visibility critical during physical de
 sign. This work presents an early-stage thermal analysis methodology joint
 l...\n\n\nJason Crop (Broadcom) and Sujyesh Aanandh Manjunthan (Synopsys)\
 n---------------------\nA Probe-Based Time-Domain Methodology for Dynamic 
 Thermal Management in Stacked-Die Architectures\n\nDynamic Thermal Managem
 ent (DTM) techniques are increasingly critical for high-power heterogeneou
 s chip designs, where sustained peak operation can lead to rapid thermal l
 imit violations. We present a dynamic, probe-based thermal methodology to 
 quantitatively evaluate settling time post peak power e...\n\n\nSumanth Su
 raneni (Annapurna Labs US Inc.), Nikhil Jayakumar (Amazon), and Sujyesh Aa
 nandh Manjunthan (Synopsys)\n---------------------\nAI-Enhanced Early Ther
 mal Aware Module Placement for 3DIC PPA Optimization\n\nWhile 3D disaggreg
 ated chiplets are viewed as the future of chip design, the approach inhere
 ntly has drawbacks in thermal performance. This is because some of the chi
 plets in a given 3D stack may not be in contact with a good heat sink. In 
 traditional 2D design methodology, a good heat sink is usual...\n\n\nYi-We
 i Chen, Chung-Ching Peng, Vivek Rajan, Chia-Yi Liou, Chih-Hsiang Yang, Kur
 t Chu, and Kuan-Ting Kuo (Intel) and Xukang Wu, Xiaohu Xu, Sonia Beghum, a
 nd Keshava Manimunda (Cadence Design Systems, Inc.)\n\nTopics: Chiplet, ED
 A\n\nSession Chair: Tim Helvey (Marvell)
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